Francesco TORTORELLA | Computer Organization
Francesco TORTORELLA Computer Organization
cod. 0612700011
COMPUTER ORGANIZATION
| 0612700011 | |
| DEPARTMENT OF INFORMATION AND ELECTRICAL ENGINEERING AND APPLIED MATHEMATICS | |
| EQF6 | |
| COMPUTER ENGINEERING | |
| 2024/2025 |
| OBBLIGATORIO | |
| YEAR OF COURSE 1 | |
| YEAR OF DIDACTIC SYSTEM 2022 | |
| SPRING SEMESTER |
| SSD | CFU | HOURS | ACTIVITY | |
|---|---|---|---|---|
| ING-INF/05 | 6 | 48 | LESSONS | |
| ING-INF/05 | 2 | 16 | EXERCISES | |
| ING-INF/05 | 1 | 8 | LAB |
| Objectives | |
|---|---|
| THE COURSE COVERS THE PRINCIPLES OF COMPUTER ORGANIZATION, THE LOW-LEVEL PROGRAMMING MODEL, THE MAIN COMPONENTS OF THE ARCHITECTURES AND THEIR PERFORMANCE MEASURES. IT ALSO INTRODUCES COMBINATORIAL AND SEQUENTIAL NETWORKS USED AS BUILDING BLOCKS OF THE MAIN ARCHITECTURAL COMPONENTS. KNOWLEDGE AND UNDERSTANDING PRINCIPLES OF COMPUTER ORGANIZATION AND LOW-LEVEL PROGRAMMING. ARCHITECTURE PERFORMANCE EVALUATION AND THEIR IMPACT ON PROGRAMS PERFORMANCE. ARCHITECTURE AND DESIGN OF COMPUTER COMPONENTS. FUNCTIONS OF BASIC COMBINATORIAL NETWORK (ADDER, MULTIPLEXER, ENCODER, DECODER). APPLYING KNOWLEDGE AND UNDERSTANDING ASSEMBLY PROGRAMMING, LOGICAL DESIGN OF THE COMPUTER BASIC BLOCKS. INTEGRATION OF HARDWARE AND SOFTWARE DESIGN. |
| Prerequisites | |
|---|---|
| THE CLASS REQUIRES KNOWLEDGE OF C PROGRAMMING. AS A STRICT PREREQUISITE, THE STUDENT MUST HAVE PASSED THE COURSE OF FOUNDATIONS OF PROGRAMMING |
| Contents | |
|---|---|
| Didactic unit 1: FUNDAMENTAL CONCEPTS AND COMPUTER LANGUAGE (LECTURE/PRACTICE/LABORATORY HOURS 20/0/8) - 1 (2 Hours Lecture): Introduction to the course. The Von Neumann model. MIPS processor programming model - 2 (2 Hours Lecture): MIPS Assembly instruction classes. Operands and addressing methods. - 3 (2 Hours Lecture): Binary representation of unsigned and signed integers. - 4 (2 Hours Lecture): Arithmetic instructions. Data transfer instructions. - 5 (2 Hours Laboratory): Operations between signed and unsigned integers in base 2. Arithmetic instructions. Translation of calculation and assignment instructions in Assembly. - 6 (2 Hours Lecture): Representation of the instructions. Logical operations - 7 (2 Hours Lecture): Jump instructions: jump and branch. Assembly selection constructs. - 8 (2 Hours Laboratory): Constructs of selection - 9 (2 Hours Lecture): Iterative Constructs in Assembly. - 10 (2 Hours Lecture): Assembler directives. Array definition and management. - 11 (2 Hours Laboratory): Iterative constructs, arrays - 12 (2 Hours Lecture): Subprograms. Instructions for calling and passing parameters through registers - 13 (2 Hours Lecture): Subprograms. Passing parameters through the stack. Register saving and restoring. - 14 (2 Hours Laboratory): Coding and execution of programs with subprograms KNOWLEDGE AND UNDERSTANDING: Principles of organization and low-level programming of a computer APPLIED KNOWLEDGE AND UNDERSTANDING: Creating programs in Assembly language Didactic unit 2: Elements of switching circuits (LECTURE/PRACTICE/LABORATORY HOURS 8/4/0) - 15 (2 Hours Lecture): Logic gates and Boolean Algebra. Boolean functions. - 16 (2 Hours Lecture): Combinational networks. Minimization and synthesis - 17 (2 Hours Practice): Synthesis of combinational networks - 18 (2 Hours Practice): Notable combinational machines (encoder / decoder. Mux / demux, adders) - 19 (2 Hours Lecture): Synchronous sequential networks: clock and synchronization methodology - 20 (2 Hours Lecture): Notable sequential machines: flip-flops and registers KNOWLEDGE AND UNDERSTANDING: operating principles of elementary combinational and sequential circuits APPLIED KNOWLEDGE AND UNDERSTANDING: Designing simple combinational circuits. Didactic unit 3: Processor architecture (LECTURE/PRACTICE/LABORATORY HOURS 8/4/0) - 21 (2 Hours Lecture): Single cycle datapath: definition of the processing unit. - 22 (2 Hours Lecture): Single cycle datapath: definition of the control unit. Clock synchronization and definition. - 23 (2 Hours Practice): Simulation of the execution of instructions on the implemented data path - 24 (2 Hours Lecture): Pipeline: hardware structure. Hazards - 25 (2 Hours Lecture): Pipeline: control unit - 26 (2 Hours Practice): Simulation of execution of instructions on pipeline. Simulation of Hazards KNOWLEDGE AND UNDERSTANDING: Architecture of a single-cycle and pipelined processor KNOWLEDGE AND UNDERSTANDING APPLIED: Recognize and predict the impact of programming choices on execution time Didactic unit 4: Memory hierarchy (LECTURE/PRACTICE/LABORATORY HOURS 6/4/0) - 27 (2 HOUR Lesson): Memory hierarchy. Direct access cache - 28 (2 Hours Lecture): Associative and set-associative cache - 29 (2 Hours Practice): Access to the cache - 30 (2 Hours Lecture): Virtual memory - 31 (2 Hours Practice): Access to the virtual memory KNOWLEDGE AND UNDERSTANDING: Operating principles of the memory hierarchy and its organization KNOWLEDGE AND UNDERSTANDING APPLIED: Recognize and predict the impact of accessing the memory hierarchy on performance. Didactic Unit 5: Input/Output (LECTURE/PRACTICE/LABORATORY HOURS 6/0/4) - 32 (2 Hours Lecture): Exceptions and interruptions - 33 (2 Hours Lecture): Input / Output. Interfaces. Memory mapped and insulated I / O. - 34 (2 Hours Lecture): Synchronization techniques (polling and interrupt). DMA - 35 (2 Hours Laboratory): Coding and execution of simple I/O drivers - 36 (2 Hours Laboratory): Coding and execution of simple I/O drivers KNOWLEDGE AND UNDERSTANDING: Organization and operating principles of the I/O system of a computer APPLIED KNOWLEDGE AND UNDERSTANDING: Create simple drivers for I/O interfaces starting from assigned specifications TOTAL HOURS OF LESSON / EXERCISE / LABORATORY 48/12/12 |
| Teaching Methods | |
|---|---|
| THE COURSE INCLUDES LECTURES AND PRACTICE SESSIONS IN THE CLASSROOM. IN THE PRACTICE SESSIONS STUDENTS ARE GIVEN PROBLEMS TO BE SOLVED UNDER THE TEACHER SUPERVISION. SOME PRACTICE SESSIONS REQUIRE THE USE OF AN ASSEMBLY PROGRAMMING ENVIRONMENT. |
| Verification of learning | |
|---|---|
| PROFICIENCY IS EVALUATED THROUGH THE MID-TERM AND THE FINAL WRITTEN TEST. IN EACH TEST STUDENTS ARE REQUIRED TO SOLVE EXERCISES SIMILAR TO THOSE THAT HAVE BEEN PRESENTED AND DISCUSSED DURING THE PRACTICE. DURING THE TESTS STUDENTS CAN USE BOOKS AND OTHER SUPPORTING MATERIAL PROVIDED BY THE INSTRUCTORS. OTHER MATERIAL AS WELL AS ELECTRONIC DEVICES FOR DATA STORING AND/OR PROCESSING ARE NOT ALLOWED. EACH PROBLEM IN A TEST IS GIVEN A MAXIMUM SCORE SUCH THAT THEIR SUM ACROSS EACH TESTS IS EQUAL TO 32. SCORES ARE GIVEN TAKING INTO ACCOUNT CORRECTNESS, COMPLETENESS AND QUALITY OF THE PROPOSED SOLUTIONS. THE COURSE FINAL SCORE IS OBTAINED BY ROUNDING THE AVERAGE OF THE SCORES ASSIGNED TO EACH TEST. STUDENTS MISSING THE INTERMEDIATE TEST OR ACHIEVING A SCORE LOWER THAN 18 WILL BE REQUIRED TO TAKE A FINAL TEST COVERING ALL THE TOPICS. THE EVALUATION CAN BE CUM LAUDE FOR STUDENTS ACHIEVING AN AVERAGE SCORE GREATER THAN 30. |
| Texts | |
|---|---|
| D.A. PATTERSON AND J.L. HENNESSY, COMPUTER AND ORGANIZATION DESIGN. THE HARDWARE/SOFTWARE INTERFACE. MIPS EDITION, MORGAN-KAUFFMANN, 6TH ED., 2020. SUPPLEMENTARY TEACHING MATERIAL WILL BE AVAILABLE ON THE UNIVERSITY E-LEARNING PLATFORM (HTTP://ELEARNING.UNISA.IT) ACCESSIBLE TO STUDENTS USING THEIR OWN UNIVERSITY CREDENTIALS. |
| More Information | |
|---|---|
| THE COURSE IS HELD IN ITALIAN |
BETA VERSION Data source ESSE3 [Ultima Sincronizzazione: 2024-11-18]
