Carmine Grasso | COMPUTER ARCHITECTURE
Carmine Grasso COMPUTER ARCHITECTURE
cod. 0512100002
COMPUTER ARCHITECTURE
| 0512100002 | |
| COMPUTER SCIENCE | |
| EQF6 | |
| COMPUTER SCIENCE | |
| 2023/2024 |
| OBBLIGATORIO | |
| YEAR OF COURSE 1 | |
| YEAR OF DIDACTIC SYSTEM 2017 | |
| AUTUMN SEMESTER |
| SSD | CFU | HOURS | ACTIVITY | |
|---|---|---|---|---|
| INF/01 | 7 | 56 | LESSONS | |
| INF/01 | 2 | 16 | EXERCISES |
| Objectives | |
|---|---|
| IN THE FRAMEWORK OF THE VON NEUMANN MODEL, THE STUDENT WILL ACQUIRE THE KNOWLEDGE OF THE IMPLEMENTATIVE METHODOLOGY OF THE SET OF BASIC ASSEMBLER INSTRUCTIONS, FACING THE STUDY OF THE HARDWARE STRUCTURE OF THE CENTRAL PROCESSING UNIT AND OF THE CONTROL UNIT ADDRESSABLE MEMORY. THROUGH THE STUDY OF THE ARITHMETIC-LOGIC UNIT, THE STUDENT WILL LEARN THE BASIC CONCEPTS FOR THE IMPLEMENTATION OF BOOLEAN FUNCTIONS THROUGH COMBINATORY NETWORKS. THE STUDY OF THE IMPLEMENTATION WILL BE COMPLETED WITH THE LEARNING OF THE BASICS FOR MEASURING AND IMPROVING HARDWARE PERFORMANCE. ABILITY TO APPLY KNOWLEDGE AND UNDERSTANDING - EXECUTION AND UNDERSTANDING OF THE TRANSLATION PROCESS IN THE ASSEMBLER OF AN ARCHITECTURE RISC OF THE BASIC BUILDINGS OF LANGUAGE C, CHOSEN AS AN EXEMPLARY OF THE PROCEDURAL LANGUAGE OF USER LEVEL; - ANALYSIS OF A COMBINATORY NETWORK AND DETERMINATION OF THE RELEVANT BOOLEAN FUNCTION IMPLEMENTED; - EXECUTION OF THE CONVERSIONS IN DECIMAL NOTATION OF THE MAIN INTERNAL REPRESENTATION FORMATS OF THE INTERIOR AND FRACTIONARY NUMBERS; - EXECUTION OF SIMPLE CALCULATIONS TO EVALUATE THE HARDWARE PERFORMANCE ACCORDING TO BOTH THE CYCLE AND THE CLOCK FREQUENCY. |
| Prerequisites | |
|---|---|
| THE STUDENT MUST NOT HAVE SPECIAL COMPUTER KNOWLEDGE. A GOOD KNOWLEDGE AS A PERSONAL COMPUTER USER CAN HELP IN THE FRAMEWORK OF SOME PARTS OF THE COURSE. KNOWLEDGE (EVEN APPROXIMATE) OF PROGRAMMING CAN HELP IN THE PART RELATING TO ASSEMBLER PROGRAMMING. |
| Contents | |
|---|---|
| 1) COMPUTER ARCHITECTURE (1 CREDIT) 2) REPRESENTATION OF THE INFORMATION (1 CREDIT) 3) DIGITAL LOGIC (1 CREDIT) 4) ASSEMBLER LANGUAGE OF A RISC MACHINE (2 CREDITS) 5) IMPLEMENTATION OF THE SINGLE CYCLE PROCESSING UNIT (1 CREDIT) 6) PERFORMANCE MEASUREMENT, PERFORMANCE IMPROVEMENT THROUGH PIPELINES (2 CREDITS) 7) MEMORY HIERARCHIES (1 CREDIT) |
| Teaching Methods | |
|---|---|
| THE COURSE CONSISTS OF LECTURES FOR 7 CFU AND TUTORIAL LESSONS FOR 2 CFU. |
| Verification of learning | |
|---|---|
| WRITTEN TEST AND ORAL EXAMINATION. THERE ARE TWO IN ITINERE TESTS THAT EXEMPT THE WRITTEN TEST. THE WRITTEN TEST AND THE IN ITINERE TESTS ARE USED TO ASSESS THE STUDENT'S ABILITY TO PRACTICE THE NOTIONS OF TEACHING THROUGH THE RESOLUTION OF SPECIFIC EXERCISES OF INFORMATION REPRESENTATION, ASSEMBLER PROGRAMMING AND COMPLEX LOGIC CIRCUIT DESIGN. THE ORAL EXAMINATION IS AIMED TO ASSESS THE GENERAL PREPARATION WITH RESPECT TO THE ENTIRE PROGRAM. |
| Texts | |
|---|---|
| DAVID PATTERSON - JOHN HENNESSY, "STRUCTURE, AND PROJECT OF COMPUTERS.", V EDITION ZANICHELLI ---- FRANCO PREPARATA, "INTRODUCTION TO THE ORGANIZATION AND DESIGN OF AN ELECTRONIC ELEBORATOR", FRANCO ANGELI ---- THE FIRST TEXT BOOK MAY POSSIBLY BE REPLACED BY THE PREVIOUS EDITION OF THE SAME: DAVID PATTERSON - JOHN HENNESSY, "STRUTTURA, ORGANIZZAZIONE E PROGETTO DEI CALCOLATORI.", IV EDIZIONE ZANICHELLI |
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