Barbara MASUCCI | COMPUTER ARCHITECTURE
Barbara MASUCCI COMPUTER ARCHITECTURE
cod. 0512100002
COMPUTER ARCHITECTURE
| 0512100002 | |
| DIPARTIMENTO DI INFORMATICA | |
| EQF6 | |
| COMPUTER SCIENCE | |
| 2020/2021 |
| OBBLIGATORIO | |
| YEAR OF COURSE 1 | |
| YEAR OF DIDACTIC SYSTEM 2017 | |
| PRIMO SEMESTRE |
| SSD | CFU | HOURS | ACTIVITY | |
|---|---|---|---|---|
| INF/01 | 7 | 56 | LESSONS | |
| INF/01 | 2 | 16 | EXERCISES |
| Objectives | |
|---|---|
| KNOWLEDGE AND UNDERSTANDING WITHIN THE FRAMEWORK OF THE VON NEUMANN MODEL, THE STUDENT WILL ACQUIRE THE KNOWLEDGE OF THE IMPLEMENTATION METHODOLOGY OF THE BASIC ASSEMBLER INSTRUCTION SET, BY ANALYSING THE HARDWARE STRUCTURE OF THE CENTRAL PROCESSING UNIT AND OF ADDRESSABLE MEMORY DEVICES. WITH THE STUDY OF THE ARITHMETIC LOGICAL UNIT, THE STUDENT WILL GET THE BASIC CONCEPTS FOR THE IMPLEMENTATION OF BOOLEAN FUNCTIONS REALISED BY COMBINATORIAL LOGICAL NETWORKS. THE STUDY OF THE IMPLEMENTATION WILL BE COMPLETED BY LEARNING THE BASICS OF HOW TO MEASURE AND IMPROVE HARDWARE PERFORMANCE. APPLYING KNOWLEDGE AND UNDERSTANDING THE STUDENT WILL ACQUIRE THE FOLLOWING APPLICATION CAPABILITIES: •EXECUTING AND UNDERSTANDING THE TRANSLATION PROCESS FROM THE BASIC CONSTRUCTS OF THE C LANGUAGE, CHOSEN AS EXAMPLE OF THE PROCEDURAL LANGUAGES AT THE USER LEVEL, TO THE ASSEMBLER INSTRUCTIONS OF A RISC ARCHITECTURE; •ANALYSING COMBINATORIAL LOGICAL NETWORKS AND BOOLEAN FUNCTIONS REALIZED BY THEM; •CONVERTING INTEGERS AND FRACTIONS FROM DECIMAL TO BINARY AND FROM BINARY TO DECIMAL; •EVALUATING HARDWARE PERFORMANCES. |
| Prerequisites | |
|---|---|
| THE STUDENT IS NOT REQUIRED TO HAVE ANY PARTICULAR KNOWLEDGE IN COMPUTER SCIENCE. A GOOD KNOWLEDGE OF PERSONAL COMPUTERS AS A USER COULD BE USEFUL. AN (EVEN APPROXIMATE) KNOWLEDGE OF PROGRAMMING COULD BE USEFUL FOR A BETTER UNDERSTANDING OF THE ASSEMBLER PROGRAMMING. |
| Contents | |
|---|---|
| 1.COMPUTER ARCHITECTURE: 1 CFU 2.INFORMATION REPRESENTATION: 1 CFU 3.DIGITAL LOGIC: 1 CFU 4.ASSEMBLER OF A RISC PROCESSOR: 2 CFUS 5.SINGLE CYCLE IMPLEMENTATION OF THE PROCESSOR: 1 CFU 6.PERFORMANCE EVALUATION, PERFORMANCE IMPROVEMENT BY PIPELINE: 2 CFUS 7.MEMORY HIERARCHIES: 1 CFU |
| Teaching Methods | |
|---|---|
| THE COURSE CONSISTS OF LECTURES FOR 7CFUS AND TUTORIAL LESSONS FOR 2 CFUS. |
| Verification of learning | |
|---|---|
| WRITTEN TEST AND ORAL EXAMINATION. STUDENTS WILL BE GIVEN THE CHANCE TO PASS TWO MIDTERMS INSTEAD OF THE WRITTEN TEST. THE WRITTEN TEST AND THE MIDTERMS ARE USED TO EVALUATE THE ABILITY OF THE STUDENT TO PUT IN PRACTICE THE DEVELOPED TOPICS THROUGH THE RESOLUTION OF EXERCISES ON INFORMATION REPRESENTATION, ASSEMBLY PROGRAMMING AND DESIGN OF COMPLEX LOGICAL CIRCUITS. ORAL EXAMINATION IS USED TO EVALUATE THE GENERAL KNOWLEDGE OF THE STUDENT WITH RESPECT TO THE ENTIRE COURSE PROGRAM. |
| Texts | |
|---|---|
| TEXTBOOKS ARE: •DAVID PATTERSON - JOHN HENNESSY, "STRUTTURA, ORGANIZZAZIONE E PROGETTO DEI CALCOLATORI", FOURTH EDITION, ZANICHELLI. •FRANCO PREPARATA, “INTRODUZIONE ALLA ORGANIZZAZIONE E ALLA PROGETTAZIONE DI UN ELABORATORE ELETTRONICO", FRANCO ANGELI. THE FIRST TEXTBOOK CAN BE SUBSTITUTED BY ITS PREVIOUS EDITION: DAVID PATTERSON - JOHN HENNESSY, "STRUTTURA, ORGANIZZAZIONE E PROGETTO DEI CALCOLATORI", THIRD EDITION, ZANICHELLI. |
BETA VERSION Data source ESSE3 [Ultima Sincronizzazione: 2022-05-23]
