Angelo GAETA | TECNOLOGIE DIGITALI

cod. 0612700110

TECNOLOGIE DIGITALI

	0612700110
	DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE ED ELETTRICA E MATEMATICA APPLICATA
	EQF6
	COMPUTER ENGINEERING
	2018/2019

PERCORSO COMUNE

	OBBLIGATORIO
	YEAR OF COURSE 2
	YEAR OF DIDACTIC SYSTEM 2017
	PRIMO SEMESTRE

TEACHING UNITS

	SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
1	CIRCUITI DIGITALI
	ING-INF/01	2	16	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
	ING-INF/01	1	8	EXERCISES	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
2	LABORATORIO DI CIRCUITI LOGICI
	ING-INF/05	1	8	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
	ING-INF/05	2	16	LAB	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS

PROFESSORS

	LUIGI DI BENEDETTO1 T Curriculum
	ANGELO GAETA2 Curriculum

	Objectives
	The course is aimed at acquiring the knowledge of the electronic technologies needed for the implementation of elementary logic networks, both combinatorial and sequential, and the ability to analyze simple logic networks based on these technologies. Knowledge and understanding Characteristics of the main logic familes. Elementary logic networks. Memory devices. ASICs. Applying knowledge and understanding Choice of a logic family. Analysis of circuits implementing elementary logic networks.

The course is aimed at acquiring the knowledge of the electronic technologies needed for the implementation of elementary logic networks, both combinatorial and sequential, and the ability to analyze simple logic networks based on these technologies.

Knowledge and understanding
Characteristics of the main logic familes. Elementary logic networks. Memory devices. ASICs.

Applying knowledge and understanding
Choice of a logic family. Analysis of circuits implementing elementary logic networks.

	Prerequisites
	In order to achieve the best results, students must know in advance: • fundamentals of electrical circuits. • fundamentals of logic networks.

	Contents
	1. Introduction to digital circuits. MOS transistors. Logic gates: NOT, AND/NAND, OR/NOR. Fan in / Fan out. CMOS logic families. 2. Design of combinatorial networks by using CMOS basic logic gates. 3. Latches and Flip-flops. Design of sequential networks by using CMOS basic logic gates. 4. Programmable logic devices: PLD e FPGA. Introduction to VHDL language. 5. Tools for design and simulation of digital systems targetted to FPGA. Design of combinatorial machines by VHDL. Implementation of combinatorial machines by FPGA. Design of sequential machines by VHDL. Implementation of sequential machines by FPGA.

Contents

1. Introduction to digital circuits. MOS transistors. Logic gates: NOT, AND/NAND, OR/NOR. Fan in / Fan out. CMOS logic families.

2. Design of combinatorial networks by using CMOS basic logic gates.

3. Latches and Flip-flops. Design of sequential networks by using CMOS basic logic gates.

4. Programmable logic devices: PLD e FPGA. Introduction to VHDL language.

5. Tools for design and simulation of digital systems targetted to FPGA.
Design of combinatorial machines by VHDL.
Implementation of combinatorial machines by FPGA.
Design of sequential machines by VHDL.
Implementation of sequential machines by FPGA.

	Teaching Methods
	The lessons will include 20h of theoretical lessons, 4h of tutorial and 14h of laboratory. Laboratory activities will involve the students in the digital design of systems learned during the theoretical and tutorial lessons, by using Xilinx environment.

	Verification of learning
	The learning level will be verified by the presentation of a project developed by using the HW/SW tools learned during the lessons and an oral interview. The interview will consists in a couple of questions about the circuit topologies and operations studied during the lesson. Completeness, correctness and clearness of the presentation will be evaluated to determine the 50% of the final grade. This last will be expressed out of thirty.

Verification of learning

The learning level will be verified by the presentation of a project developed by using the HW/SW tools learned during the lessons and an oral interview. The interview will consists in a couple of questions about the circuit topologies and operations studied during the lesson. Completeness, correctness and clearness of the presentation will be evaluated to determine the 50% of the final grade. This last will be expressed out of thirty.

	Texts
	1. J. M. Rabaey, A. Chandrakasan, B. Nikolic “circuiti integrati digitali: l’ottica del progettista”, Pearson/Prentice-Hall. 2. Books in electronic format and slides about CMOS logic circuits and VHDL language will be provided during the lessons. 3. Manuals of HW/SW tools.

	More Information
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BETA VERSION Data source ESSE3 [Ultima Sincronizzazione: 2019-10-21]

Angelo GAETA | TECNOLOGIE DIGITALI