ROSALBA LIGUORI | DIGITAL TECHNOLOGIES

cod. 0612700110

DIGITAL TECHNOLOGIES

	0612700110
	DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE ED ELETTRICA E MATEMATICA APPLICATA
	EQF6
	COMPUTER ENGINEERING
	2019/2020

PERCORSO COMUNE Cohort 2018/2019

	OBBLIGATORIO
	YEAR OF COURSE 2
	YEAR OF DIDACTIC SYSTEM 2017
	PRIMO SEMESTRE

TEACHING UNITS

	SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
1	CIRCUITI DIGITALI (Modulo di TECNOLOGIE DIGITALI)
	ING-INF/01	2	16	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
	ING-INF/01	1	8	EXERCISES	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
2	LABORATORIO DI CIRCUITI LOGICI (Modulo di TECNOLOGIE DIGITALI)
	ING-INF/05	1	8	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
	ING-INF/05	2	16	LAB	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS

PROFESSORS

	ROSALBA LIGUORI1 T Curriculum
	ANGELO GAETA2 Curriculum

	Objectives
	THE COURSE AIMS TO ACQUIRE THE KNOWLEDGE OF THE ELECTRONIC TECHNOLOGIES NECESSARY FOR THE REALIZATION OF ELEMENTARY COMBINATIONAL AND SEQUENTIAL LOGICAL NETWORKS AND THE ABILITY TO ANALYZE SIMPLE LOGICAL NETWORKS BASED ON THESE TECHNOLOGIES. THE EXERCISE ACTIVITY CONSISTS OF PERFORMING NUMERICAL EXERCISES AND THE LABORATORY FORESEES THE DEVELOPMENT OF DIGITAL SYSTEMS. KNOWLEDGE AND UNDERSTANDING ABILITY THE STUDENT WILL BE ABLE TO ANALYZE: - THE STATIC AND DYNAMIC CHARACTERISTICS OF THE MAIN LOGICAL FAMILIES. - ELEMENTARY LOGIC NETWORKS. - MEMORY DEVICES. - AN ASIC CIRCUIT. KNOWLEDGE AND UNDERSTANDING UNDERSTANDING - CHOICE OF A LOGICAL FAMILY. - ANALYSIS OF CIRCUIT IMPLEMENTATIONS OF ELEMENTARY LOGIC NETWORKS. AUTONOMY OF JUDGMENT THE STUDENT WILL BE SUCCEED IN: - IDENTIFY THE PERFORMANCE PARAMETERS OF THE DEVICES; - IDENTIFY THE MOST APPROPRIATE METHODS FOR THE ANALYSIS AND SYNTHESIS OF MEDIUM COMPLEXITY CIRCUITS; - KEEP IN MIND THE LIMITS FOR A "SAFE" OPERATION OF THE COMPONENTS; - COMBINE PRACTICE AND MODELS FOR NETWORK SIZING. COMMUNICATION SKILLS THE STUDENT WILL ACQUIRE A TECHNICAL-SCIENTIFIC LANGUAGE IN THE WRITTEN AND ORAL EXPOSITION AND IN THE COMMUNICATION WITH THE WORK GROUP DURING THE DEVELOPMENT OF THE DESIGN OF THE DIGITAL SYSTEM. ABILITY TO LEARN DUE TO THE NEED TO TRANSMIT TO THE STUDENT THE ABILITY TO ANALYZE THE EFFECTS OF THE PERFORMANCE LIMITS OF THE CIRCUITS IN THE DIGITAL SYSTEM, HE/SHE WILL BE AWARE OF THE CONTINUOUS EVOLUTION OF THESE SYSTEMS AND THE NEED FOR CONTINUOUS AUTONOMOUS LEARNING.

THE COURSE AIMS TO ACQUIRE THE KNOWLEDGE OF THE ELECTRONIC TECHNOLOGIES NECESSARY FOR THE REALIZATION OF ELEMENTARY COMBINATIONAL AND SEQUENTIAL LOGICAL NETWORKS AND THE ABILITY TO ANALYZE SIMPLE LOGICAL NETWORKS BASED ON THESE TECHNOLOGIES. THE EXERCISE ACTIVITY CONSISTS OF PERFORMING NUMERICAL EXERCISES AND THE LABORATORY FORESEES THE DEVELOPMENT OF DIGITAL SYSTEMS.

KNOWLEDGE AND UNDERSTANDING ABILITY
THE STUDENT WILL BE ABLE TO ANALYZE:
- THE STATIC AND DYNAMIC CHARACTERISTICS OF THE MAIN LOGICAL FAMILIES.
- ELEMENTARY LOGIC NETWORKS.
- MEMORY DEVICES.
- AN ASIC CIRCUIT.

KNOWLEDGE AND UNDERSTANDING UNDERSTANDING
- CHOICE OF A LOGICAL FAMILY.
- ANALYSIS OF CIRCUIT IMPLEMENTATIONS OF ELEMENTARY LOGIC NETWORKS.

AUTONOMY OF JUDGMENT
THE STUDENT WILL BE SUCCEED IN:
- IDENTIFY THE PERFORMANCE PARAMETERS OF THE DEVICES;
- IDENTIFY THE MOST APPROPRIATE METHODS FOR THE ANALYSIS AND SYNTHESIS OF MEDIUM COMPLEXITY CIRCUITS;
- KEEP IN MIND THE LIMITS FOR A "SAFE" OPERATION OF THE COMPONENTS;
- COMBINE PRACTICE AND MODELS FOR NETWORK SIZING.

COMMUNICATION SKILLS
THE STUDENT WILL ACQUIRE A TECHNICAL-SCIENTIFIC LANGUAGE IN THE WRITTEN AND ORAL EXPOSITION AND IN THE COMMUNICATION WITH THE WORK GROUP DURING THE DEVELOPMENT OF THE DESIGN OF THE DIGITAL SYSTEM.

ABILITY TO LEARN
DUE TO THE NEED TO TRANSMIT TO THE STUDENT THE ABILITY TO ANALYZE THE EFFECTS OF THE PERFORMANCE LIMITS OF THE CIRCUITS IN THE DIGITAL SYSTEM, HE/SHE WILL BE AWARE OF THE CONTINUOUS EVOLUTION OF THESE SYSTEMS AND THE NEED FOR CONTINUOUS AUTONOMOUS LEARNING.

	Prerequisites
	IN ORDER TO ACHIEVE THE BEST RESULTS, STUDENTS MUST KNOW IN ADVANCE: • FUNDAMENTALS OF LOGIC NETWORKS.

	Contents
	1. INTRODUCTION TO DIGITAL CIRCUITS. MOS TRANSISTORS. LOGIC GATES: NOT, AND/NAND, OR/NOR. FAN IN / FAN OUT. CMOS LOGIC FAMILIES. (HOURS THEORY: 6, EXERC.: 3) 2. DESIGN OF COMBINATORIAL NETWORKS BY USING CMOS BASIC LOGIC GATES. (HOURS THEORY: 3, EXERC.: 3) 3. LATCHES AND FLIP-FLOPS. DESIGN OF SEQUENTIAL NETWORKS BY USING CMOS BASIC LOGIC GATES. (HOURS THEORY: 3, EXERC.: 1) 4. PROGRAMMABLE LOGIC DEVICES: PLD E FPGA. INTRODUCTION TO VHDL LANGUAGE. (HOURS THEORY: 4) 5. TOOLS FOR DESIGN AND SIMULATION OF DIGITAL SYSTEMS TARGETTED TO FPGA. (HOURS THEORY: 8, LAB.: 16) DESIGN OF COMBINATORIAL MACHINES BY VHDL. IMPLEMENTATION OF COMBINATORIAL MACHINES BY FPGA. DESIGN OF SEQUENTIAL MACHINES BY VHDL. IMPLEMENTATION OF SEQUENTIAL MACHINES BY FPGA.

Contents

1. INTRODUCTION TO DIGITAL CIRCUITS. MOS TRANSISTORS. LOGIC GATES: NOT, AND/NAND, OR/NOR. FAN IN / FAN OUT. CMOS LOGIC FAMILIES. (HOURS THEORY: 6, EXERC.: 3)

2. DESIGN OF COMBINATORIAL NETWORKS BY USING CMOS BASIC LOGIC GATES. (HOURS THEORY: 3, EXERC.: 3)

3. LATCHES AND FLIP-FLOPS. DESIGN OF SEQUENTIAL NETWORKS BY USING CMOS BASIC LOGIC GATES. (HOURS THEORY: 3, EXERC.: 1)

4. PROGRAMMABLE LOGIC DEVICES: PLD E FPGA. INTRODUCTION TO VHDL LANGUAGE. (HOURS THEORY: 4)

5. TOOLS FOR DESIGN AND SIMULATION OF DIGITAL SYSTEMS TARGETTED TO FPGA. (HOURS THEORY: 8, LAB.: 16)
DESIGN OF COMBINATORIAL MACHINES BY VHDL.
IMPLEMENTATION OF COMBINATORIAL MACHINES BY FPGA.
DESIGN OF SEQUENTIAL MACHINES BY VHDL.
IMPLEMENTATION OF SEQUENTIAL MACHINES BY FPGA.

	Teaching Methods
	THE LECTURES ARE DIVIDED AS FOLLOWS: -THEORETICAL LECTURES (HOURS 24/ CFU 3); -CLASSROOM EXERCISES (HOURS 8/ CFU 1): SOLUTIONS OF NUMERICAL EXERCISES; -LABORATORIES EXERCISES (HOURS 16/ CFU 2): DEVELOPMENT OF DIGITAL SYSTEMS, SHOWN DURING THE THEORETICAL LECTURES, USING XILINX SOFTWARE TOOLS AND VHDL.

	Verification of learning
	THE EVALUATION OF THE ACHIEVEMENT OF THE SET OBJECTIVES WILL TAKE PLACE THROUGH A WRITTEN TEST AND AN ORAL TEST. THE FINAL GRADE WILL BE DETERMINED BY THE AVERAGE OF ORAL AND WRITTEN GRADES AND WILL BE EXPRESSED IN THIRTIETHS (THE MINIMUM GRADE CORRESPONDS TO "18" AND THE MAXIMUM TO "30 E LAUDE"). "30 E LAUDE" MAY BE GIVEN IN THE CASE OF A WRITTEN TEST EVALUATED WITH A AND AN ORAL TEST THAT FULLY SATISFIES THE EVALUATION CRITERIA. DURING THE COURSE, PARTIAL WRITTEN EXONERATIVE TESTS ARE SCHEDULED. THE WRITTEN TEST INVOLVES THE PERFORMANCE OF A TASK REQUIRING THE IMPLEMENTATION OF A COMBINATORIAL NETWORK IN CMOS TECHNOLOGY, THE CALCULATION OF THE STATIC AND DYNAMIC PERFORMANCE OF A LOGICAL NETWORK AND THE STUDY OF A SEQUENTIAL NETWORK. FROM THE WRITTEN TEST THE STUDENT WILL HAVE ACCESS TO THE ORAL TEST WITH GRADES A, B, C, D OR E, WHILE THE MARK F DOES NOT ALLOW ADMISSION. THE COPY OF THE WRITTEN PAPER IS DELIVERED WITH THE ERRORS MARKED AND ANY SUGGESTIONS FOR SOLUTIONS. THE ORAL EXAM CONSISTS OF THE PRESENTATION OF A PAPER AND QUESTIONS RELEVANT TO THE WORK ITSELF AND TO THE THEORETICAL PART CARRIED OUT IN "THE FPGA DEVELOPMENT AND SIMULATION TOOLS". THE PAPER FORESEES THE REALIZATION OF A DIGITAL SYSTEM USING VHDL AND XILINX TOOL, ASSIGNED DURING THE COURSE. THE TECHNICAL DISCUSSION REPORT WILL BE PROVIDED TO THE TEACHER WHO WILL BE ASSESSED ON THE BASIS OF TECHNICAL CORRECTNESS AND COMPLETENESS.

Verification of learning

THE EVALUATION OF THE ACHIEVEMENT OF THE SET OBJECTIVES WILL TAKE PLACE THROUGH A WRITTEN TEST AND AN ORAL TEST. THE FINAL GRADE WILL BE DETERMINED BY THE AVERAGE OF ORAL AND WRITTEN GRADES AND WILL BE EXPRESSED IN THIRTIETHS (THE MINIMUM GRADE CORRESPONDS TO "18" AND THE MAXIMUM TO "30 E LAUDE"). "30 E LAUDE" MAY BE GIVEN IN THE CASE OF A WRITTEN TEST EVALUATED WITH A AND AN ORAL TEST THAT FULLY SATISFIES THE EVALUATION CRITERIA. DURING THE COURSE, PARTIAL WRITTEN EXONERATIVE TESTS ARE SCHEDULED.

THE WRITTEN TEST INVOLVES THE PERFORMANCE OF A TASK REQUIRING THE IMPLEMENTATION OF A COMBINATORIAL NETWORK IN CMOS TECHNOLOGY, THE CALCULATION OF THE STATIC AND DYNAMIC PERFORMANCE OF A LOGICAL NETWORK AND THE STUDY OF A SEQUENTIAL NETWORK. FROM THE WRITTEN TEST THE STUDENT WILL HAVE ACCESS TO THE ORAL TEST WITH GRADES A, B, C, D OR E, WHILE THE MARK F DOES NOT ALLOW ADMISSION. THE COPY OF THE WRITTEN PAPER IS DELIVERED WITH THE ERRORS MARKED AND ANY SUGGESTIONS FOR SOLUTIONS.

THE ORAL EXAM CONSISTS OF THE PRESENTATION OF A PAPER AND QUESTIONS RELEVANT TO THE WORK ITSELF AND TO THE THEORETICAL PART CARRIED OUT IN "THE FPGA DEVELOPMENT AND SIMULATION TOOLS". THE PAPER FORESEES THE REALIZATION OF A DIGITAL SYSTEM USING VHDL AND XILINX TOOL, ASSIGNED DURING THE COURSE. THE TECHNICAL DISCUSSION REPORT WILL BE PROVIDED TO THE TEACHER WHO WILL BE ASSESSED ON THE BASIS OF TECHNICAL CORRECTNESS AND COMPLETENESS.

	Texts
	1. BOOK: J. M. RABAEY, A. CHANDRAKASAN, B. NIKOLIC “CIRCUITI INTEGRATI DIGITALI: L’OTTICA DEL PROGETTISTA”, PEARSON/PRENTICE-HALL. 2. TEACHING MATERIAL PROVIDED BY THE TEACHER DURING THE COURSE ON CMOS LOGIC AND VHDL LANGUAGE IN THE FORM OF SLIDES AND TEXTS IN ELECTRONIC FORMAT. 3. MANUALI DEI TOOL HW/SW.

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ROSALBA LIGUORI | DIGITAL TECHNOLOGIES