Ettore NAPOLI | SYSTEM ON CHIP
Ettore NAPOLI SYSTEM ON CHIP
cod. 0622700114
SYSTEM ON CHIP
| 0622700114 | |
| DEPARTMENT OF INFORMATION AND ELECTRICAL ENGINEERING AND APPLIED MATHEMATICS | |
| EQF7 | |
| COMPUTER ENGINEERING | |
| 2023/2024 |
| YEAR OF COURSE 2 | |
| YEAR OF DIDACTIC SYSTEM 2022 | |
| SPRING SEMESTER |
| SSD | CFU | HOURS | ACTIVITY | |
|---|---|---|---|---|
| ING-INF/01 | 3 | 24 | LESSONS | |
| ING-INF/01 | 3 | 24 | EXERCISES |
| Objectives | |
|---|---|
| THE COURSE INTRODUCES THE DESIGN OF DIGITAL INTEGRATED CIRCUITS TO BE USED AS HIGH-PERFORMANCE HARDWARE COPROCESSORS FOR ELECTRONIC SYSTEMS THAT INCLUDE ONE OR MORE PROCESSORS, MULTIPLE CONFIGURABLE PERIPHERALS, AND PROGRAMMABLE LOGIC. THESE SYSTEMS ARE DEDICATED TO APPLICATIONS WITH TIGHT CONSTRAINTS IN TERMS OF PERFORMANCE AND ARE USED, FOR EXAMPLE, FOR THE DESIGN OF ELECTRONIC SYSTEMS DEDICATED TO VIDEO PROCESSING, ARTIFICIAL INTELLIGENCE, DATA COMPRESSION/DECOMPRESSION. THE COURSE PRESENTS THE DESIGN PROBLEMS AND THE RELEVANT RESOLUTION METHODS. THE COURSE TAKES THE FRONT END OF DIGITAL DESIGN, WITH EMPHASIS ON THE DESIGN OF ARCHITECTURE FOR DATA PROCESSING AND THEIR DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES (HDL). THE COURSE ALSO PRESENTS THE DESIGN TECHNIQUES OF THE ARCHITECTURE OF SOC SYSTEMS AND THE METHODOLOGIES FOR TESTING AND DESIGNING A SOC SYSTEM THAT USES HARDWARE COPROCESSORS. |
| Prerequisites | |
|---|---|
| THE COURSE ASSUMES THE KNOWLEDGE OF: THE BASIC NOTIONS OF LOGICAL, COMBINATORIAL AND SEQUENTIAL NETWORKS, THE C LANGUAGE, AND THE BASIC NOTIONS OF EMBEDDED SYSTEMS. |
| Contents | |
|---|---|
| DIDACTIC UNIT 1: DESIGN OF DIGITAL CIRCUITS (LECTURE/PRACTICE/LABORATORY HOURS 14/1/6) - 1 (3 HOURS LECTURE): EVOLUTION OF THE TECHNOLOGIES FOR THE IMPLEMENTATION OF DIGITAL CIRCUITS AND MOTIVATION FOR THE USE OF FPGAS. DESIGN FLOW FOR DIGITAL CIRCUITS AND FPGAS. THE FRONT-END AND THE BACK-END. STRUCTURE OF A COMMERCIALLY AVAILABLE FPGA. - 2 (2 HOURS LECTURE) THE HDL VERILOG LANGUAGE. BASIC CONSTRUCTS. DESCRIPTION OF DECODER AND PRIORITY ENCODER. TOP LEVEL AND DETAILED SCHEMATIC OF A DIGITAL CIRCUIT. THE INPUT AND OUTPUT PORTS. STRUCTURE OF THE MODULE. CONTINUOUS ASSIGNMENT AND DESCRIPTION OF BOOLEAN FUNCTIONS. ARRAY. INTERNAL SIGNALS. LOGICAL VALUES AND BOOLEAN OPERATORS IN VERILOG. - 3 (1 HOUR LABORATORY): QUARTUSII DEVELOPMENT SYSTEM. DESCRIPTION, SIMULATION, AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS. - 4 (1 HOUR LECTURE): NUMBERS IN VERILOG, HIERARCHY (PORTS AND SIGNALS), CONCATENATION, PROCEDURAL BLOCKS, HDL DESCRIPTION OF A FLIP FLOP. - 5 (1 HOUR LABORATORY): IMPLEMENTATION OF COMBINATIONAL CIRCUITS ON DEMONSTRATION BOARD. THE 7-SEGMENT DISPLAY DECODER. - 6 (2 HOURS LECTURE): THE MULTIPLEXER IN VERILOG LANGUAGE. THE LUTS IN VERILOG LANGUAGE AND THE COMPARATOR CIRCUIT. SIGNED AND FIXED POINT NUMBERS AND THEIR NOTATION. TRUNCATION AND ROUNDING. ADDITION, SUBTRACTION AND MULTIPLICATION OPERATIONS. - 7 (1 HOUR LABORATORY): IMPLEMENTATION OF AN ARITHMETIC CIRCUIT. 8-BIT ADDER WITH OVERFLOW. - 8 (2 HOURS LECTURE): HDL DESCRIPTION AND IMPLEMENTATION OF SEQUENTIAL CIRCUITS. FF WITH SYNCHRONOUS AND ASYNCHRONOUS RESET. FF ENABLED. REGISTERS, SHIFT REGISTERS, COUNTERS. - 9 (1 HOUR LABORATORY): EXPERIMENT ON THE IMPLEMENTATION OF SEQUENTIAL CIRCUIT, THE JOHNSON COUNTER. - 10 (2 HOURS LECTURE): HDL DESCRIPTION AND FSM IMPLEMENTATION. - 11 (2 HOURS LABORATORY): CIRCUIT FOR CALCULATING THE MAXIMUM BETWEEN TWO SIGNALS, CIRCUIT THAT BLINKS AN LED. - 12 (2 HOURS LECTURE): TIMING OF SEQUENTIAL CIRCUITS. SECOND COUNTER CIRCUIT DESIGN. - 13 (1 HOUR PRACTICE): TEST AND SOLUTION OF THE EXERCISES PROPOSED FOR THE DESIGN OF SEQUENTIAL CIRCUITS. EXERCISES ON THE TIMING OF SYNCHRONOUS CIRCUITS. KNOWLEDGE AND UNDERSTANDING: THE DESIGN FLOW FOR THE DESIGN OF DIGITAL ELECTRONIC CIRCUITS. THE VERILOG HDL LANGUAGE. APPLIED KNOWLEDGE AND UNDERSTANDING: DESIGN OF THE BLOCK DIAGRAM OF A DIGITAL CIRCUIT. DESCRIBING A DIGITAL CIRCUIT USING THE VERILOG HDL LANGUAGE. SIMULATION AND TEST OF A DIGITAL CIRCUIT. DIDACTIC UNIT 2: ARCHITECTURE OF A SYSTEM ON CHIP (HOURS LESSON / EXERCISE / LABORATORY 3/0/4) - 1 (3 HOURS LECTURE): INTRODUCTION TO THE ZYNQ SOC. SOCS AND THE USE OF BUSES. TYPES OF BUSES. AMBA BUS: PROTOCOL, CHANNELS, AND EXAMPLES. - 2 (2 HOURS LABORATORY): IMPLEMENTATION OF THE CIRCUIT ON THE PL SECTION OF THE ZYNQ. - 3 (2 HOURS LABORATORY): SOFTWARE APPLICATION PROJECT IMPLEMENTED ON THE PS SECTION OF THE ZYNQ. KNOWLEDGE AND UNDERSTANDING: STRUCTURE OF A SOC. THE AMBA BUS. APPLIED KNOWLEDGE AND UNDERSTANDING: DESIGN OF A SOC SYSTEM USING THE SOFTWARE AND HARDWARE SECTIONS. DIDACTIC UNIT 3: SOC DESIGN (HOURS LECTURE/PRACTICE/LABORATORY 9/3/8) - 1 (2 HOURS LECTURE): PROJECT ON ZYNQ SOC USING PS, PL, AND THE AXI LITE CONNECTION VIA AXI GPIO COMPONENT. TESTBENCH FOR SIMULATING THE ZYNQ SOC. - 2 (4 HOURS PRACTICE): SOC DESIGN USING THE PL SECTION AND THE PS SECTION. HW/SW APPLICATION PROJECT WITH AXI LITE CONNECTION. - 3 (2 HOURS LECTURE): IP PROJECT WITH AXI LITE CONNECTION TO THE ARM PROCESSOR. - 4 (3 HOURS LABORATORY): IP PROJECT FOR PATTERN SEARCH AND COMPARISON WITH THE PERFORMANCE OF THE SW IMPLEMENTATION. - 5 (3 HOURS LESSON): USING A DMA IN THE ZYNQ SYSTEM. STRUCTURE OF THE DMA AND METHODS OF USE WITH POLLING AND WITH INTERRUPTS. - 6 (3 HOURS LABORATORY): POLLING AND INTERRUPT FOR THE USE OF DMA. TESTING AND USE OF THE INTEGRATED LOGIC ANALYZER. - 7 (2 HOURS LECTURE): AXI STREAM INTERFACE. IP PROJECT WITH STREAMING INTERFACE. - 8 (2 HOURS LABORATORY): EXAMPLE OF USE OF THE AXI STREAM INTERFACE CONNECTED TO A DMA. KNOWLEDGE AND UNDERSTANDING: THE STRUCTURE OF A SOC. THE FLOW FOR THE DESIGN OF A SOC SYSTEM. THE AMBA COMMUNICATION BUS. THE STRUCTURE OF AN HW COPROCESSOR AND HOW IT IS INTERFACED WITH THE PROCESSOR. TEST METHODOLOGIES FOR SOC SYSTEMS. APPLIED KNOWLEDGE AND UNDERSTANDING: DESIGNING AND DRAWING THE SCHEME OF A SOC SYSTEM. IMPLEMENT SIMPLE SOFTWARE SECTIONS FOR MANAGING A SOC SYSTEM. TESTING A SOC. TOTAL HOURS LECTURE/PRACTICE/LABORATORY 26/4/18 |
| Teaching Methods | |
|---|---|
| THE COURSE INCLUDES THEORETICAL LESSONS (26 HOURS), EXERCISES (4 HOURS), AND LABORATORY WORK (18 HOURS). DURING LABORATORY HOURS THE VIVADO AND VITIS SOFTWARE TOOLS ARE USED AND THE CIRCUITS MADE ON ZYBO-Z720 PROTOTYPE BOARDS ARE IMPLEMENTED AND TESTED. THE LABORATORY INCLUDES AND EXPANDS THE COURSE CONTENT COVERED UNTIL THAT TIME AND IS FUNDAMENTAL FOR THE ACQUISITION OF THE DESIGN SKILLS OF DIGITAL CIRCUITS AND SOC SYSTEMS STARTING FROM THE SPECS. |
| Verification of learning | |
|---|---|
| THE FINAL EVALUATION IS CONDUCTED BY MEANS OF A MEDIUM-TERM TEST AND A FINAL TEST. THE MEDIUM-TERM TEST IS STRUCTURED IN OPEN ANSWER QUESTIONS AIMED AT ASSESSING THE UNDERSTANDING OF THE TOPICS AND THE ABILITY TO DESIGN SIMPLE DIGITAL CIRCUITS. THE FINAL WRITTEN TEST, IN THE FORM OF A PROJECT, INCLUDES THE DESIGN OF AN EXTENSION OF ONE OF THE SOC SYSTEMS PRESENTED DURING THE LECTURES AND SOME METHODOLOGICAL QUESTIONS WITH OPEN ANSWERS. THE ORAL EXAM CONSISTS OF THE DISCUSSION OF THE FINAL WORK. EACH TEST IS ASSESSED IN THIRTIES. THE FINAL MARK IS GIVEN BY THE AVERAGE WEIGHT OF THE SINGLE TESTS, WHERE THE WEIGHT OF THE INTERMEDIATE TEST IS 40%, THE FINAL TEST IS 40%, AND THE FINAL DISCUSSION IS 20%. |
| Texts | |
|---|---|
| E. NAPOLI - PROGETTO DI CIRCUITI DIGITALI E IMPLEMENTAZIONE SU FPGA ED. ESCULAPIO 2023 ISBN: 9788893853507 THE TEACHING MATERIAL IS AVAILABLE ON THE UNIVERSITY E-LEARNING PLATFORM (HTTP://ELEARNING.UNISA.IT) ACCESSIBLE TO STUDENTS USING THEIR OWN UNIVERSITY CREDENTIALS. |
| More Information | |
|---|---|
| THE COURSE IS DELIVERED IN ITALIAN LANGUAGE. |
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