Ettore NAPOLI | DIGITAL CIRCUITS AND SYSTEMS

cod. 0612700138

DIGITAL CIRCUITS AND SYSTEMS

	0612700138
	DEPARTMENT OF INFORMATION AND ELECTRICAL ENGINEERING AND APPLIED MATHEMATICS
	EQF6
	COMPUTER ENGINEERING
	2024/2025

CURRICULUM SYSTEMS

	OBBLIGATORIO
	YEAR OF COURSE 2
	YEAR OF DIDACTIC SYSTEM 2022
	SPRING SEMESTER

TEACHING UNITS

SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
ING-INF/01	3	24	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
ING-INF/01	2	16	EXERCISES	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
ING-INF/01	1	8	LAB	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS

	Objectives
	THE COURSE INTRODUCES TO THE DESIGN OF VLSI DIGITAL INTEGRATED CIRCUITS WHICH PROVIDE THE PROCESSING CAPACITY TO COMPUTER SYSTEMS AND COMMUNICATION SYSTEMS. THE COURSE PRESENTS THE DESIGN PROBLEMS AND THE RELEVANT RESOLUTION METHODS. IN PARTICULAR, THE TEACHING DETAILS THE FRONT END OF THE DIGITAL DESIGN FLOW, WITH EMPHASIS ON ARCHITECTURE DESIGN FOR DATA PROCESSING AND THEIR DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES.

THE COURSE INTRODUCES TO THE DESIGN OF VLSI DIGITAL INTEGRATED CIRCUITS WHICH PROVIDE THE PROCESSING CAPACITY TO COMPUTER SYSTEMS AND COMMUNICATION SYSTEMS. THE COURSE PRESENTS THE DESIGN PROBLEMS AND THE RELEVANT RESOLUTION METHODS. IN PARTICULAR, THE TEACHING DETAILS THE FRONT END OF THE DIGITAL DESIGN FLOW, WITH EMPHASIS ON ARCHITECTURE DESIGN FOR DATA PROCESSING AND THEIR DESCRIPTION USING HARDWARE DESCRIPTION LANGUAGES.

	Prerequisites
	THE COURSE ASSUMES THE KNOWLEDGE OF: BASIC NOTIONS OF LOGICAL, COMBINATORIAL, AND SEQUENTIAL NETWORKS. THE TEACHING REQUIRES THE FOLLOWING LECTURES: CALCOLATORI ELETTRONICI, ELETTROTECNICA.

	Contents
	DIDACTIC UNIT 1: FUNDAMENTALS OF DIGITAL ELECTRONICS (HOURS LECTURE/PRACTICE/LABORATORY 7/0/0) - 1 (1 HOUR LECTURE): RECALLS ON BOOLEAN LOGIC. - 2 (2 HOURS LECTURE): THE MOS AND THE CMOS INVERTER. - 3 (2 HOURS LECTURE): THE CMOS LOGIC STYLE FOR THE REALIZATION OF COMBINATORIAL FUNCTIONS AND MEMORY ELEMENTS. - 4 (2 HOURS LECTURE): PERFORMANCE PARAMETERS FOR DIGITAL ELECTRONIC CIRCUITS. AREA, SPEED, POWER DISSIPATION. KNOWLEDGE AND UNDERSTANDING: THE STRUCTURE OF A VLSI CIRCUIT AND PERFORMANCE EVALUATION. APPLIED KNOWLEDGE AND UNDERSTANDING: DRAWING THE TRANSISTOR LEVEL CIRCUIT DIAGRAM FOR THE IMPLEMENTATION OF A SIMPLE COMBINATORIAL OR SEQUENTIAL FUNCTION. DIDACTIC UNIT 2: DESIGN FLOW FOR DIGITAL ELECTRONIC CIRCUITS. TECHNOLOGIES FOR THE IMPLEMENTATION OF DIGITAL ELECTRONIC CIRCUITS (HOURS LECTURE/PRACTICE/LABORATORY 4/0/1) - 1 (2 HOURS LECTURE): TECHNOLOGIES FOR THE IMPLEMENTATION OF DIGITAL ELECTRONIC CIRCUITS. EVOLUTION OF THE DESIGN AND MOTIVATION FOR THE USE OF FPGAS. - 2 (2 HOURS LECTURE): DESIGN FLOW FOR DIGITAL CIRCUITS AND FPGA-FRONT END AND BACK END. STRUCTURE OF A COMMERCIALLY AVAILABLE FPGA AND FPGA. - 3 (1 HOUR LABORATORY): THE LOGICAL SYNTHESIS. KNOWLEDGE AND UNDERSTANDING: THE DESIGN FLOW FOR DIGITAL ELECTRONIC CIRCUITS. STRUCTURE OF AN FPGA DEVICE. APPLIED KNOWLEDGE AND UNDERSTANDING: PLANNING THE DESIGN OF A DIGITAL ELECTRONIC CIRCUIT. READ AND UNDERSTAND THE DATASHEET OF AN FPGA DEVICE. DIDACTIC UNIT 3: THE VERILOG HDL LANGUAGE FOR THE DESCRIPTION, SYNTHESIS, AND TESTING OF DIGITAL ELECTRONIC CIRCUITS. (HOURS LECTURE/PRACTICE/LABORATORY 13/5/13) - 1 (2 HOURS LECTURE): THE VERILOG LANGUAGE. LOGICAL LEVELS, NUMBERS, BOOLEAN OPERATORS AND CONCATENATION. HIERARCHY. - 2 (3 HOURS LABORATORY): INTRODUCTION TO THE SOFTWARE TOOLS. IMPLEMENTATION OF THE 7-SEGMENT DISPLAY DECODER. TESTING AND PIN PLACEMENT FOR THE DECODER OFR THE 7-SEGMENT DISPLAY. - 3 (2 HOURS LECTURE): PROCEDURAL BLOCKS. IMPLEMENTATION OF MUX, DECODER AND ENCODER. PRIORITY ENCODER. IMPLEMENTATION OF TRUTH TABLES. EXAMPLE OF A COMPLETE COMBINATORIAL DESIGN FOR THE IMPLEMENTATION OF THE GLUE LOGIC BETWEEN PROCESSOR AND MEMORIES. - 4 (1 HOUR LECTURE): TESTBENCH FOR COMBINATIONAL CIRCUITS. - 5 (3 HOURS LABORATORY): IMPLEMENTATION OF COMBINATIONAL CIRCUITS. - 6 (1 HOUR PRACTICE): EXERCISE ON COMBINATORIAL CIRCUITS. - 7 (2 HOURS LECTURE): DESCRIPTION OF ARITHMETIC CIRCUITS. TRUNCATION, ROUNDING. IMPLEMENTATION OF ADDERS, MULTIPLIERS, AND MAC, IN VERILOG LANGUAGE. - 8 (2 HOURS LABORATORY): IMPLEMENTATION OF ARITHMETIC CIRCUITS. - 9 (2 HOUR PRACTICE): EXERCISE ON ARITHMETIC CIRCUITS. - 10 (2 HOURS LECTURE): DESCRIPTION OF SEQUENTIAL CIRCUITS: FLIP FLOPS, REGISTERS, AND SHIFT REGISTERS. - 11 (1 HOUR LECTURE): TESTBENCH FOR SEQUENTIAL CIRCUITS. - 12 (3 HOURS LABORATORY): IMPLEMENTATION OF SEQUENTIAL CIRCUITS. - 13 (1 HOUR PRACTICE): EXERCISE ON SEQUENTIAL CIRCUITS. - 14 (3 HOURS LECTURE): FINITE STATE MACHINES OF THE MOORE TYPE AND OF THE MEALY TYPE. VERILOG DESCRIPTION OF FINITE STATE MACHINES. - 15 (2 HOURS LABORATORY): IMPLEMENTATION OF FINITE STATE MACHINES. - 16 (1 HOUR PRACTICE): EXERCISE ON FINITE STATE MACHINES. KNOWLEDGE AND UNDERSTANDING: THE HDL VERILOG LANGUAGE. THE TOOLS FOR THE LOGIC SYNTHESIS AND FOR THE SIMULATION OF A DIGITAL CIRCUIT. APPLIED KNOWLEDGE AND UNDERSTANDING: DRAWING THE BLOCK DIAGRAM FOR A DIGITAL CIRCUIT. HDL DESCRIPTION OF A DIGITAL CIRCUIT. DESIGN OF A TESTBENCH AND SIMULATION OF THE BEHAVIOR OF A DIGITAL CIRCUIT. DIDACTIC UNIT 4: PERFORMANCE OF DIGITAL ELECTRONIC CIRCUITS. (HOURS LECTURE/PRACTICE/LABORATORY 4/1/0) - 1 (2 HOURS LECTURE): TIMING FOR SEQUENTIAL CIRCUITS. IMPOSITION OF TIMING CONSTRAINTS FOR THE SYNTHESIS OF A DIGITAL ELECTRONIC CIRCUIT. - 2 (1 HOURS OF PRACTICE): SETUP TIME AND HOLD TIME CONSTRAINTS. - 3 (2 HOURS LECTURE): ESTIMATION AND SIMULATION OF THE POWER DISSIPATION FOR DIGITAL CIRCUITS IMPLEMENTED ON FPGA. KNOWLEDGE AND UNDERSTANDING: THE METHODS AND TECHNIQUES FOR THE SYNCHRONIZATION OF DIGITAL CIRCUITS. TOOLS FOR THE ESTIMATION OF THE SPEED AND THE POWER DISSIPATION. APPLIED KNOWLEDGE AND UNDERSTANDING: CALCULATION OF THE DESIGN MARGINS ON THE SPEED OF A DIGITAL COURCUIT. ESTIMATION OF THE POWER DISSIPATED BY A DIGITAL CIRCUIT. DETERMINE THE PERFORMANCES OF A DIGITAL CIRCUIT.

Contents

DIDACTIC UNIT 1: FUNDAMENTALS OF DIGITAL ELECTRONICS
(HOURS LECTURE/PRACTICE/LABORATORY 7/0/0)

- 1 (1 HOUR LECTURE): RECALLS ON BOOLEAN LOGIC.

- 2 (2 HOURS LECTURE): THE MOS AND THE CMOS INVERTER.

- 3 (2 HOURS LECTURE): THE CMOS LOGIC STYLE FOR THE REALIZATION OF COMBINATORIAL FUNCTIONS AND MEMORY ELEMENTS.

- 4 (2 HOURS LECTURE): PERFORMANCE PARAMETERS FOR DIGITAL ELECTRONIC CIRCUITS. AREA, SPEED, POWER DISSIPATION.

KNOWLEDGE AND UNDERSTANDING: THE STRUCTURE OF A VLSI CIRCUIT AND PERFORMANCE EVALUATION.

APPLIED KNOWLEDGE AND UNDERSTANDING: DRAWING THE TRANSISTOR LEVEL CIRCUIT DIAGRAM FOR THE IMPLEMENTATION OF A SIMPLE COMBINATORIAL OR SEQUENTIAL FUNCTION.

DIDACTIC UNIT 2: DESIGN FLOW FOR DIGITAL ELECTRONIC CIRCUITS.
TECHNOLOGIES FOR THE IMPLEMENTATION OF DIGITAL ELECTRONIC CIRCUITS
(HOURS LECTURE/PRACTICE/LABORATORY 4/0/1)

- 1 (2 HOURS LECTURE): TECHNOLOGIES FOR THE IMPLEMENTATION OF DIGITAL ELECTRONIC CIRCUITS. EVOLUTION OF THE DESIGN AND MOTIVATION FOR THE USE OF FPGAS.

- 2 (2 HOURS LECTURE): DESIGN FLOW FOR DIGITAL CIRCUITS AND FPGA-FRONT END AND BACK END. STRUCTURE OF A COMMERCIALLY AVAILABLE FPGA AND FPGA.

- 3 (1 HOUR LABORATORY): THE LOGICAL SYNTHESIS.

KNOWLEDGE AND UNDERSTANDING: THE DESIGN FLOW FOR DIGITAL ELECTRONIC CIRCUITS. STRUCTURE OF AN FPGA DEVICE.

APPLIED KNOWLEDGE AND UNDERSTANDING: PLANNING THE DESIGN OF A DIGITAL ELECTRONIC CIRCUIT. READ AND UNDERSTAND THE DATASHEET OF AN FPGA DEVICE.

DIDACTIC UNIT 3: THE VERILOG HDL LANGUAGE FOR THE DESCRIPTION, SYNTHESIS, AND TESTING OF DIGITAL ELECTRONIC CIRCUITS.
(HOURS LECTURE/PRACTICE/LABORATORY 13/5/13)

- 1 (2 HOURS LECTURE): THE VERILOG LANGUAGE. LOGICAL LEVELS, NUMBERS, BOOLEAN OPERATORS AND CONCATENATION. HIERARCHY.

- 2 (3 HOURS LABORATORY): INTRODUCTION TO THE SOFTWARE TOOLS. IMPLEMENTATION OF THE 7-SEGMENT DISPLAY DECODER. TESTING AND PIN PLACEMENT FOR THE DECODER OFR THE 7-SEGMENT DISPLAY.

- 3 (2 HOURS LECTURE): PROCEDURAL BLOCKS. IMPLEMENTATION OF MUX, DECODER AND ENCODER. PRIORITY ENCODER. IMPLEMENTATION OF TRUTH TABLES. EXAMPLE OF A COMPLETE COMBINATORIAL DESIGN FOR THE IMPLEMENTATION OF THE GLUE LOGIC BETWEEN PROCESSOR AND MEMORIES.

- 4 (1 HOUR LECTURE): TESTBENCH FOR COMBINATIONAL CIRCUITS.

- 5 (3 HOURS LABORATORY): IMPLEMENTATION OF COMBINATIONAL CIRCUITS.

- 6 (1 HOUR PRACTICE): EXERCISE ON COMBINATORIAL CIRCUITS.

- 7 (2 HOURS LECTURE): DESCRIPTION OF ARITHMETIC CIRCUITS. TRUNCATION, ROUNDING. IMPLEMENTATION OF ADDERS, MULTIPLIERS, AND MAC, IN VERILOG LANGUAGE.

- 8 (2 HOURS LABORATORY): IMPLEMENTATION OF ARITHMETIC CIRCUITS.

- 9 (2 HOUR PRACTICE): EXERCISE ON ARITHMETIC CIRCUITS.

- 10 (2 HOURS LECTURE): DESCRIPTION OF SEQUENTIAL CIRCUITS: FLIP FLOPS, REGISTERS, AND SHIFT REGISTERS.

- 11 (1 HOUR LECTURE): TESTBENCH FOR SEQUENTIAL CIRCUITS.

- 12 (3 HOURS LABORATORY): IMPLEMENTATION OF SEQUENTIAL CIRCUITS.

- 13 (1 HOUR PRACTICE): EXERCISE ON SEQUENTIAL CIRCUITS.

- 14 (3 HOURS LECTURE): FINITE STATE MACHINES OF THE MOORE TYPE AND OF THE MEALY TYPE. VERILOG DESCRIPTION OF FINITE STATE MACHINES.

- 15 (2 HOURS LABORATORY): IMPLEMENTATION OF FINITE STATE MACHINES.

- 16 (1 HOUR PRACTICE): EXERCISE ON FINITE STATE MACHINES.

KNOWLEDGE AND UNDERSTANDING: THE HDL VERILOG LANGUAGE. THE TOOLS FOR THE LOGIC SYNTHESIS AND FOR THE SIMULATION OF A DIGITAL CIRCUIT.

APPLIED KNOWLEDGE AND UNDERSTANDING: DRAWING THE BLOCK DIAGRAM FOR A DIGITAL CIRCUIT. HDL DESCRIPTION OF A DIGITAL CIRCUIT. DESIGN OF A TESTBENCH AND SIMULATION OF THE BEHAVIOR OF A DIGITAL CIRCUIT.

DIDACTIC UNIT 4: PERFORMANCE OF DIGITAL ELECTRONIC CIRCUITS.
(HOURS LECTURE/PRACTICE/LABORATORY 4/1/0)

- 1 (2 HOURS LECTURE): TIMING FOR SEQUENTIAL CIRCUITS. IMPOSITION OF TIMING CONSTRAINTS FOR THE SYNTHESIS OF A DIGITAL ELECTRONIC CIRCUIT.

- 2 (1 HOURS OF PRACTICE): SETUP TIME AND HOLD TIME CONSTRAINTS.

- 3 (2 HOURS LECTURE): ESTIMATION AND SIMULATION OF THE POWER DISSIPATION FOR DIGITAL CIRCUITS IMPLEMENTED ON FPGA.

KNOWLEDGE AND UNDERSTANDING: THE METHODS AND TECHNIQUES FOR THE SYNCHRONIZATION OF DIGITAL CIRCUITS. TOOLS FOR THE ESTIMATION OF THE SPEED AND THE POWER DISSIPATION.

APPLIED KNOWLEDGE AND UNDERSTANDING: CALCULATION OF THE DESIGN MARGINS ON THE SPEED OF A DIGITAL COURCUIT. ESTIMATION OF THE POWER DISSIPATED BY A DIGITAL CIRCUIT. DETERMINE THE PERFORMANCES OF A DIGITAL CIRCUIT.

	Teaching Methods
	THE COURSE INCLUDES THEORETICAL LESSONS (30 HOURS), LABORATORY LESSONS (13 HOURS), AND EXERCISES (5 HOURS). DURING THE LABORATORY HOURS THE CIRCUITS ARE IMPLEMENTED USING QUARTUSII AND MODELSIM SOFTWARE TOOLS. THE CIRCUITS ARE THEN EXPERIMENTALLY TESTED USING PROTOTYPE BOARDS. DURING THE EXERCISES, STUDENTS ARE ASSIGNED A DESIGN PROBLEM TO BE SOLVED WITH THE HELP OF THE TEACHER. THE EXERCISES INCLUDE ALL THE TEACHING CONTENTS COVERED UP TO THAT POINT AND ARE INSTRUMENTAL TO THE ACQUISITION OF THE SKILLS OF DESIGNING AND BUILDING LOGIC CIRCUITS STARTING FROM THE SPECIFICATIONS.

Teaching Methods

THE COURSE INCLUDES THEORETICAL LESSONS (30 HOURS), LABORATORY LESSONS (13 HOURS), AND EXERCISES (5 HOURS). DURING THE LABORATORY HOURS THE CIRCUITS ARE IMPLEMENTED USING QUARTUSII AND MODELSIM SOFTWARE TOOLS. THE CIRCUITS ARE THEN EXPERIMENTALLY TESTED USING PROTOTYPE BOARDS. DURING THE EXERCISES, STUDENTS ARE ASSIGNED A DESIGN PROBLEM TO BE SOLVED WITH THE HELP OF THE TEACHER. THE EXERCISES INCLUDE ALL THE TEACHING CONTENTS COVERED UP TO THAT POINT AND ARE INSTRUMENTAL TO THE ACQUISITION OF THE SKILLS OF DESIGNING AND BUILDING LOGIC CIRCUITS STARTING FROM THE SPECIFICATIONS.

	Verification of learning
	THE FINAL EVALUATION IS CONDUCTED BY MEANS OF A MEDIUM-TERM TEST AND A FINAL TEST. THE MEDIUM-TERM TEST IS DIVIDED IN OPEN-ENDED QUESTIONS AIMED AT ASCERTAINING THE UNDERSTANDING OF THE TOPICS AND THE ABILITY TO DESIGN SIMPLE DIGITAL CIRCUITS. THE FINAL WRITTEN TEST (REPORT) INCLUDES THE DESIGN OF A COMPLETE DIGITAL CIRCUIT AND SOME METHODOLOGICAL QUESTIONS WITH OPEN ANSWERS. THE ORAL EXAM CONSISTS IN THE DISCUSSION OF THE FINAL REPORT. EACH TEST IS GRADED OUT OF THIRTY. THE FINAL GRADE IS GIVEN BY THE WEIGHTED AVERAGE OF THE INDIVIDUAL TESTS, WHERE THE WEIGHT OF THE MEDIUM TERM TEST IS 40%, THAT OF THE FINAL TEST IS 40%, AND THE FINAL DISCUSSION IS 20%.

Verification of learning

THE FINAL EVALUATION IS CONDUCTED BY MEANS OF A MEDIUM-TERM TEST AND A FINAL TEST.
THE MEDIUM-TERM TEST IS DIVIDED IN OPEN-ENDED QUESTIONS AIMED AT ASCERTAINING THE UNDERSTANDING OF THE TOPICS AND THE ABILITY TO DESIGN SIMPLE DIGITAL CIRCUITS.
THE FINAL WRITTEN TEST (REPORT) INCLUDES THE DESIGN OF A COMPLETE DIGITAL CIRCUIT AND SOME METHODOLOGICAL QUESTIONS WITH OPEN ANSWERS. THE ORAL EXAM CONSISTS IN THE DISCUSSION OF THE FINAL REPORT. EACH TEST IS GRADED OUT OF THIRTY. THE FINAL GRADE IS GIVEN BY THE WEIGHTED AVERAGE OF THE INDIVIDUAL TESTS, WHERE THE WEIGHT OF THE MEDIUM TERM TEST IS 40%, THAT OF THE FINAL TEST IS 40%, AND THE FINAL DISCUSSION IS 20%.

	Texts
	E. NAPOLI “PROGETTO DI CIRCUITI DIGITALI E IMPLEMENTAZIONE SU FPGA”, ED. ESCULAPIO, 2024. ISBN: 9788893853507

	More Information
	THE COURSE IS DELIVERED IN ITALIAN LANGUAGE.

Lessons Timetable

BETA VERSION Data source ESSE3 [Ultima Sincronizzazione: 2025-02-19]

Ettore NAPOLI | DIGITAL CIRCUITS AND SYSTEMS