Luca GRECO | Logic Networks
Luca GRECO Logic Networks
cod. 0612700008
LOGIC NETWORKS
| 0612700008 | |
| DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE ED ELETTRICA E MATEMATICA APPLICATA | |
| EQF6 | |
| COMPUTER ENGINEERING | |
| 2019/2020 |
| OBBLIGATORIO | |
| YEAR OF COURSE 1 | |
| YEAR OF DIDACTIC SYSTEM 2017 | |
| SECONDO SEMESTRE |
| SSD | CFU | HOURS | ACTIVITY | ||
|---|---|---|---|---|---|
| RETI LOGICHE | |||||
| ING-INF/05 | 5 | 40 | LESSONS | ||
| ING-INF/05 | 1 | 8 | EXERCISES | ||
| RETI LOGICHE | |||||
| ING-INF/01 | 1 | 8 | EXERCISES | ||
| ING-INF/01 | 2 | 16 | LAB | ||
| Objectives | |
|---|---|
| THIS COURSE PROVIDES A MODERN INTRODUCTION TO LOGIC DESIGN AND THE BASIC BUILDING BLOCKS USED IN DIGITAL SYSTEMS, IN PARTICULAR DIGITAL COMPUTERS. IT STARTS WITH A DISCUSSION OF COMBINATIONAL LOGIC. THE SECOND PART OF THE COURSE DEALS WITH SEQUENTIAL CIRCUITS: FLIP-FLOPS AND SYNTHESIS OF SEQUENTIAL CIRCUITS. KNOWLEDGE AND UNDERSTANDING INFORMATION AND ITS REPRESENTATION. BINARY-DECIMAL CODES. BOOLEAN AND SWITCHING ALGEBRA. LOGIC GATES. EXPRESSIONS AND BINARY FUNCTIONS. CANONICAL FORMS, GRAPHICS AND TABULAR MINIMIZATION ACCORDING TO QUINE-MCCLUSKEY AND PETRICK. COMBINATIONAL CIRCUITS: ANALYSIS AND SYNTHESIS, ANALYSIS AND SYNTHESIS, NAND-NAND AND NOR-NOR IMPLEMENTATIONS. HAZARDS. COMBINATIONAL COMPONENTS: ADDER, MULTIPLEXER, DEMULTIPLEXER. SYNCHRONOUS SEQUENTIAL CIRCUITS: FINITE STATE AUTOMATA, MEALY AND MOORE REPRESENTATION, SYNTHESIS AND MINIMIZATION, MEALY-MOORE AND MOORE-MEALY TRANSFORMATION, LATCH, FLIP-FLOP RS, D, JK AND T. REGISTERS AND COUNTERS. PROGRAMMABLE LOGIC DEVICES: PLD AND FPGA. INTRODUCTION TO VHDL LANGUAGE. APPLYING KNOWLEDGE AND UNDERSTANDING STUDENTS WILL BE ABLE TO DESIGN COMBINATIONAL CIRCUITS. MOREOVER, THEY WILL BE ABLE TO USE STATE MACHINE DIAGRAMS TO DESIGN FINITE STATE MACHINES USING VARIOUS TYPES OF FLIP-FLOPS AND COMBINATIONAL CIRCUITS WITH PRESCRIBED FUNCTIONALITY. FINALLY, STUDENTS WILL BE ABLE TO EVALUATE THE FUNCTIONAL BEHAVIOR OF LOGIC CIRCUITS. COMMUNICATION SKILLS STUDENTS WILL BE ABLE TO EXPRESS THEMSELVES EFFECTIVELY WITHIN THE LOGIC CIRCUITS DESIGN CONTEXT. LEARNING SKILLS STUDENTS WILL BE ABLE TO APPLY THE ACQUIRED KNOWLEDGE TO CONTESTS DIFFERENT FROM THE ONES EXPLORED IN THIS COURSE. MOREOVER, THEY WILL BE ABLE TO DEEPEN THE ARGUMENTS LEARNED BY USING BOTH TEXTBOOKS DIFFERENT FROM THE ONES HERE PROPOSED AND BY ACCESSING RESOURCES WORLDWIDE. |
| Prerequisites | |
|---|---|
| THE COURSE ASSUMES NO PROGRAMMING BACKGROUND. |
| Contents | |
|---|---|
| BASIC CONCEPTS (4H LECTURE, 2H PRACTICE) DIGITAL SYSTEMS, INFORMATION AND ITS REPRESENTATION. BINARY-DECIMAL CODES. BCD CODE, VARIABLE LENGTH CODES, HUFFMAN CODES, HAMMING CODE, GRAY CODE, EXCESS-3 CODE, ERROR CORRECTION CODES. BOOLEAN ALGEBRA (8H LECTURE, 4H PRACTICE) BOOLEAN AND SWITCHING ALGEBRA. FUNDAMENTAL THEOREMS. LOGICAL OPERATORS. BINARY EXPRESSIONS. TRUTH TABLE. EQUIVALENT AND COMPLEMENT EXPRESSION. PRINCIPLE OF DUALITY, GENERALIZED DE MORGAN'S THEOREM, SHANNON'S THEOREMS. THE BINARY FUNCTIONS. CANONICAL FORMS. THEOREM OF THE COMBINATION. THE MINIMIZATION BY ALGEBRAIC MANIPULATIONS AND IN GRAPHICAL FORM ACCORDING TO KARNAUGH. MINIMIZATION IN TABULAR FORM ACCORDING TO QUINE-MCCLUSKEY. COMBINATIORIAL CIRCUITS (4H LECTURE, 2H PRACTICE) THE ANALYSIS AND SYNTHESIS OF COMBINATORIAL NETWORKS. IMPLEMENTATIONS NAND-NAND AND NOR-NOR. EXAMPLES: COMPARATOR, BCD ENCODER, MULTIPLEXER, DEMULTIPLEXER. HALF-ADDER. ITERATIVE COMBINATORIAL NETWORKS: ADDERS AND SUBTRACTORS, 2-COMPLEMENT. HAZARDS: CLASSIFICATION AND ELIMINATION. SEQUENTIAL CIRCUITS (8H LECTURE, 4H PRACTICE) MODELS OF SYNCHRONOUS CIRCUITS, THE DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS. MEMORY ELEMENTS: ASYNCHRONOUS BISTABLES AND LATCH. SYNCHRONISM. FLIP-FLOP RS, D, JK AND T: PULSE-TRIGGERED, EDGE-TRIGGERED AND MASTER-SLAVE. REGISTERS AND COUNTERS. FINITE STATE AUTOMATA (8H LECTURE, 4H PRACTICE) SYNCHRONOUS SEQUENTIAL LOGIC AND FINITE STATE AUTOMATA. THE REPRESENTATION OF FINITE STATE AUTOMATA. THE STRUCTURAL MODELS. STATE DIAGRAM AND FLOW CHART TABLE. THE MINIMIZATION OF THE INTERNAL STATES OF AN AUTOMATON. SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS. PROGRAMMABLE LOGIC DEVICES: PLD AND FPGA. (8H PRACTICE,16H LABORATORY) INTRODUCTION TO VHDL LANGUAGE. DEVELOPMENT AND SIMULATION TOOLS FOR FPGAS. DESIGN IN VHDL OF COMBINATORIAL MACHINES. IMPLEMENTATION OF COMBINATORIAL MACHINES ON FPGA. VHDL DESIGN OF SYNCHRONOUS SEQUENTIAL MACHINES. REALIZATION OF SYNCHRONOUS SEQUENTIAL MACHINES ON FPGA. |
| Teaching Methods | |
|---|---|
| THE COURSE IS STRUCTURED AS FOLLOWS: LECTURES (32H), PRACTISE (24H) AND LABORATORY (16H). DURING THE PRACTISE, SEVERAL EXERCISES ARE PROPOSED AND DISCUSSED AND STUDENTS ARE ASKED TO DESIGN SPECIFIC CIRCUITS IN ORDER TO SOLVE THE PROBLEMS PROPOSED DURING THE LECTURES AND THE PRACTISE. THE EXERCISES DEALS WITH ALL THE ARGUMENTS DISCUSSED WITHIN THE PREVIOUS LECTURES AND ARE DESIGNED TO STRENGTHEN THE DESIGN SKILLS OF LOGIC CIRCUITS. |
| Verification of learning | |
|---|---|
| LEARNING SKILLS WILL BE CHECKED BY MEANS OF A WRITTEN MIDTERM EXAM CONCERNING COMMUTATION ALGEBRA AND COMBINATORIAL SYNTHESIS AIMED TO ASSESS THE DESIGN SKILLS BY USING THE FUNCTIONAL PROPERTIES OF PREDEFINED COMBINATORIAL CIRCUITS AND A FINAL WRITTEN EXAM AT THE END OF THE COURSE DEALING WITH THE DESIGN OF A SEQUENTIAL CIRCUIT BY MEANS OF STATE FINITE AUTOMATA AND FLIP-FLOPS, VHDL IMPLEMENTATIONS AND A NUMBER OF METHODOLOGICAL QUESTIONS. ORAL EXAMINATION CONSISTS IN AN ORAL DISCUSSION ABOUT THE WRITTEN ASSESSMENT WITH THE AIM TO ASSESS THE LEARNING SKILLS ACHIEVED. THE FINAL GRADE IS THE WEIGHTED AVERAGE OF THE INDIVIDUAL TESTS, WHERE MIDTERM EXAM WEIGHTS 40%, FINAL EXAM 40% AND ORAL EXAMINATION 20%. |
| Texts | |
|---|---|
| M. MORRIS MANO, CHARLES R. KIME: RETI LOGICHE, IV EDIZIONE, PEARSON - PRENTICE HALL, 2008. ADDITIONAL MATERIAL IS AVAILABLE ON THE COURSE WEBSITE. |
| More Information | |
|---|---|
| COMPULSORY ATTENDANCE. TEACHING IS IN ITALIAN. |
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