Luca GRECO | Logic Networks

cod. 0612700008

LOGIC NETWORKS

	0612700008
	DIPARTIMENTO DI INGEGNERIA DELL'INFORMAZIONE ED ELETTRICA E MATEMATICA APPLICATA
	EQF6
	COMPUTER ENGINEERING
	2020/2021

CURRICULUM SYSTEMS

	OBBLIGATORIO
	YEAR OF COURSE 1
	YEAR OF DIDACTIC SYSTEM 2017
	SECONDO SEMESTRE

TEACHING UNITS

	SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
1	RETI LOGICHE (MODULO 1)
	ING-INF/05	5	40	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
	ING-INF/05	1	8	EXERCISES	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
2	RETI LOGICHE (MODULO 2)
	ING-INF/01	1	8	EXERCISES	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS
	ING-INF/01	2	16	LAB	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS

PROFESSORS

	FRANCESCO MOSCATO1 T Curriculum
	LUCA GRECO1 Curriculum
	ETTORE NAPOLI2 Curriculum

	Objectives
	THE COURSE INTRODUCES THE DESIGN OF THE COMBINATORIAL AND SEQUENTIAL LOGIC CIRCUITS THAT ARE THE FUNDAMENTAL COMPONENTS OF DIGITAL SYSTEMS, PRESENTING THE PROBLEMS AND THEIR SOLUTION METHODOLOGIES. IN PARTICULAR, THE TEACHING INCLUDES THE ARGUMENTS RELATED TO LOGIC CIRCUITS, PROVIDING THE METHODOLOGIES AND PROJECT TECHNIQUES NECESSARY FOR THE REALIZATION AND OPTIMIZATION OF COMBINATORIAL AND SEQUENTIAL CIRCUITS AT VARIOUS LEVELS OF COMPLEXITY. KNOWLEDGE AND UNDERSTANDING SKILLS AT THE END OF THE COURSE THE STUDENT KNOWS: 1. BASIC CONCEPTS ABOUT LOGICAL NETWORKS AND BOOLEAN AND SWITCHING ALGEBRA. LOGICAL PORTS. EXPRESSIONS AND BINARY FUNCTIONS. CANONICAL FORMS. ALGEBRAIC AND GRAPHICS MINIMIZATION. 2. COMBINATIONAL LOGIC CIRCUITS: ANALYSIS AND SYNTHESIS, ALEE, NAND-NAND AND NOR-NOR IMPLEMENTATIONS. ALEE. REMARKABLE COMBINED NETWORKS: SUMMATORS, DECODER, MULTIPLEXER. 3. SYNCHRONOUS SEQUENTIAL NETWORKS: FINITE STATES AUTOMATONS, STATE CONCEPT, MEALY/MOORE MACHINE, MEMORY ELEMENTS: ASYNCHRONOUS AND LATCH BEAPS, SYNCHRONOUS SIGNAL, FLIP-FLOP D, JK E T TO LEVEL, ON FRONT AND MASTER-SLAVE, SYNCHRONOUS SEQUENTIAL NETWORK SUMMARY 4. INTRODUCTION TO VHDL LANGUAGE, PROGRAMMING ELEMENTS IN VHDL, COMBINING NETWORKS IN VHDL, SEQUENTIAL NETWORKS IN VHDL, FINISHED STATE AUTOMATONS IN VHDL. APPLIED KNOWLEDGE AND UNDERSTANDING SKILLS AT THE END OF THE COURSE, THE STUDENT IS ABLE TO: DESIGN COMBINATORIAL LOGIC CIRCUITS. DESIGN SEQUENTIAL NETWORKS USING FINITE STATE MACHINE AND VARIOUS TYPES OF FLIP-FLOPS AND COMBINATORIAL CIRCUITS WITH BUILT-IN FEATURES. EVALUATE THE FUNCTIONAL CHARACTERISTICS OF LOGICAL CIRCUITS. DESCRIBE, SIMULATE, AND SYNTHESIZE A COMBINATORIAL AND/OR SEQUENTIAL NETWORK IN VHDL LANGUAGE. AUTONOMY OF JUDGMENT KNOW HOW TO EVALUATE THE ORGANIZATIONAL AND DESIGN ASPECTS OF HARDWARE COMPUTING SYSTEMS. KNOW HOW TO IDENTIFY THE MOST APPROPRIATE METHODS TO DESIGN AND BUILD LOGIC CIRCUITS. COMMUNICATION SKILLS KNOW HOW TO ORALLY EXPOSE AN ARGUMENT RELATED TO THE DESIGN METHODOLOGIES OF LOGICAL NETWORKS. ABILITY TO LEARN KNOW HOW TO APPLY THE ACQUIRED KNOWLEDGE TO DIFFERENT CONTEXTS AND DEEPEN THE TOPICS COVERED USING ADDITIONAL MATERIALS.

THE COURSE INTRODUCES THE DESIGN OF THE COMBINATORIAL AND SEQUENTIAL LOGIC CIRCUITS THAT ARE THE FUNDAMENTAL COMPONENTS OF DIGITAL SYSTEMS, PRESENTING THE PROBLEMS AND THEIR SOLUTION METHODOLOGIES. IN PARTICULAR, THE TEACHING INCLUDES THE ARGUMENTS RELATED TO LOGIC CIRCUITS, PROVIDING THE METHODOLOGIES AND PROJECT TECHNIQUES NECESSARY FOR THE REALIZATION AND OPTIMIZATION OF COMBINATORIAL AND SEQUENTIAL CIRCUITS AT VARIOUS LEVELS OF COMPLEXITY.

KNOWLEDGE AND UNDERSTANDING SKILLS

AT THE END OF THE COURSE THE STUDENT KNOWS:

1. BASIC CONCEPTS ABOUT LOGICAL NETWORKS AND BOOLEAN AND SWITCHING ALGEBRA. LOGICAL PORTS. EXPRESSIONS AND BINARY FUNCTIONS. CANONICAL FORMS. ALGEBRAIC AND GRAPHICS MINIMIZATION.
2. COMBINATIONAL LOGIC CIRCUITS: ANALYSIS AND SYNTHESIS, ALEE, NAND-NAND AND NOR-NOR IMPLEMENTATIONS. ALEE. REMARKABLE COMBINED NETWORKS: SUMMATORS, DECODER, MULTIPLEXER.
3. SYNCHRONOUS SEQUENTIAL NETWORKS: FINITE STATES AUTOMATONS, STATE CONCEPT, MEALY/MOORE MACHINE, MEMORY ELEMENTS: ASYNCHRONOUS AND LATCH BEAPS, SYNCHRONOUS SIGNAL, FLIP-FLOP D, JK E T TO LEVEL, ON FRONT AND MASTER-SLAVE, SYNCHRONOUS SEQUENTIAL NETWORK SUMMARY
4. INTRODUCTION TO VHDL LANGUAGE, PROGRAMMING ELEMENTS IN VHDL, COMBINING NETWORKS IN VHDL, SEQUENTIAL NETWORKS IN VHDL, FINISHED STATE AUTOMATONS IN VHDL.

APPLIED KNOWLEDGE AND UNDERSTANDING SKILLS

AT THE END OF THE COURSE, THE STUDENT IS ABLE TO:

DESIGN COMBINATORIAL LOGIC CIRCUITS.
DESIGN SEQUENTIAL NETWORKS USING FINITE STATE MACHINE AND VARIOUS TYPES OF FLIP-FLOPS AND COMBINATORIAL CIRCUITS WITH BUILT-IN FEATURES.
EVALUATE THE FUNCTIONAL CHARACTERISTICS OF LOGICAL CIRCUITS.
DESCRIBE, SIMULATE, AND SYNTHESIZE A COMBINATORIAL AND/OR SEQUENTIAL NETWORK IN VHDL LANGUAGE.

AUTONOMY OF JUDGMENT

KNOW HOW TO EVALUATE THE ORGANIZATIONAL AND DESIGN ASPECTS OF HARDWARE COMPUTING SYSTEMS. KNOW HOW TO IDENTIFY THE MOST APPROPRIATE METHODS TO DESIGN AND BUILD LOGIC CIRCUITS.

COMMUNICATION SKILLS
KNOW HOW TO ORALLY EXPOSE AN ARGUMENT RELATED TO THE DESIGN METHODOLOGIES OF LOGICAL NETWORKS.

ABILITY TO LEARN
KNOW HOW TO APPLY THE ACQUIRED KNOWLEDGE TO DIFFERENT CONTEXTS AND DEEPEN THE TOPICS COVERED USING ADDITIONAL MATERIALS.

	Prerequisites
	NOTHING

	Contents
	BASIC CONCEPTS (2H LESSON, 2H EXERCISE) INFORMATION AND ITS REPRESENTATION. BINARY ENCODING AND TWO’S COMPLEMENT OPERATIONS. BOOLEAN ALGEBRA (10H LESSON, 6H EXERCISE) BOOLEAN ALGEBRA. FUNDAMENTAL THEOREMS. LOGICAL OPERATORS. BINARY EXPRESSIONS. CHARACTERISTIC NUMBER AND TRUTH TABLE. EQUIVALENT EXPRESSIONS AND COMPLEMENT. DE MORGAN'S GENERALIZED THEOREM, SHANNON THEOREMS. BINARY FUNCTIONS. CANONICAL FORMS. COMBINATION THEOREM. THE ALGEBRAIC AND KARNAUGH GRAPHICAL MINIMIZATION. COMBINATORIAL CIRCUITS (6H LESSON, 2H EXERCISE) THE ANALYSIS AND SYNTHESIS OF COMBINATORIAL CIRCUITS. NAND-NAND AND NOR-NOR IMPLEMENTATIONS. EXAMPLES: MULTIPLEXER, DECODER. ITERATIVE COMBINATORIAL NETWORKS: ADDER. ALEE: CLASSIFICATION AND ELIMINATION. SEQUENTIAL CIRCUITS (8H LESSON, 4H EXERCISE) INTRODUCTION TO SYNCHRONOUS SEQUENTIAL CIRCUITS. MEMORY ELEMENTS: ASYNCHRONOUS AND LATCH BISTABLES, SYNCHRONICITY SIGNAL, FLIP-FLOP RS, D, JK AND T LEVEL, ON THE FRONT AND MASTER-SLAVE. FLIP-FLOPS. THE DESIGN OF SYNCHRONOUS SEQUENTIAL NETWORKS. FINITE STATE MACHINES (8H LESSON, 12H EXERCISE) SYNCHRONOUS SEQUENTIAL CIRCUITS AND FINITE-STATE MACHINE, THE REPRESENTATION OF FINITE-STATE MACHINE. STRUCTURAL MODELS. STATE DIAGRAM AND FLOW TABLE. THE MINIMIZATION OF THE INTERNAL STATES OF A FINITE STATE MACHINE. SUMMARY OF SYNCHRONOUS SEQUENTIAL CIRCUITS. INTRODUCTION TO THE VHDL LANGUAGE (6H LESSON, 6H EXERCISE) DEVELOPMENT AND SIMULATION TOOLS FOR FPGA. PROGRAMMING ELEMENTS IN VHDL. DESIGN IN VHDL OF COMBINATORIAL CIRCUITS. DESIGN SYNCHRONOUS SEQUENTIAL CIRCUITS IN VHDL.

Contents

BASIC CONCEPTS (2H LESSON, 2H EXERCISE)

INFORMATION AND ITS REPRESENTATION. BINARY ENCODING AND TWO’S COMPLEMENT OPERATIONS.

BOOLEAN ALGEBRA (10H LESSON, 6H EXERCISE)

BOOLEAN ALGEBRA. FUNDAMENTAL THEOREMS. LOGICAL OPERATORS. BINARY EXPRESSIONS. CHARACTERISTIC NUMBER AND TRUTH TABLE. EQUIVALENT EXPRESSIONS AND COMPLEMENT. DE MORGAN'S GENERALIZED THEOREM, SHANNON THEOREMS. BINARY FUNCTIONS. CANONICAL FORMS. COMBINATION THEOREM. THE ALGEBRAIC AND KARNAUGH GRAPHICAL MINIMIZATION.

COMBINATORIAL CIRCUITS (6H LESSON, 2H EXERCISE)

THE ANALYSIS AND SYNTHESIS OF COMBINATORIAL CIRCUITS. NAND-NAND AND NOR-NOR IMPLEMENTATIONS. EXAMPLES: MULTIPLEXER, DECODER. ITERATIVE COMBINATORIAL NETWORKS: ADDER. ALEE: CLASSIFICATION AND ELIMINATION.

SEQUENTIAL CIRCUITS (8H LESSON, 4H EXERCISE)

INTRODUCTION TO SYNCHRONOUS SEQUENTIAL CIRCUITS. MEMORY ELEMENTS: ASYNCHRONOUS AND LATCH BISTABLES, SYNCHRONICITY SIGNAL, FLIP-FLOP RS, D, JK AND T LEVEL, ON THE FRONT AND MASTER-SLAVE. FLIP-FLOPS. THE DESIGN OF SYNCHRONOUS SEQUENTIAL NETWORKS.

FINITE STATE MACHINES (8H LESSON, 12H EXERCISE)

SYNCHRONOUS SEQUENTIAL CIRCUITS AND FINITE-STATE MACHINE, THE REPRESENTATION OF FINITE-STATE MACHINE. STRUCTURAL MODELS. STATE DIAGRAM AND FLOW TABLE. THE MINIMIZATION OF THE INTERNAL STATES OF A FINITE STATE MACHINE. SUMMARY OF SYNCHRONOUS SEQUENTIAL CIRCUITS.

INTRODUCTION TO THE VHDL LANGUAGE (6H LESSON, 6H EXERCISE)

DEVELOPMENT AND SIMULATION TOOLS FOR FPGA. PROGRAMMING ELEMENTS IN VHDL. DESIGN IN VHDL OF COMBINATORIAL CIRCUITS. DESIGN SYNCHRONOUS SEQUENTIAL CIRCUITS IN VHDL.

	Teaching Methods
	TEACHING INCLUDES THEORETICAL LESSONS (40H) AND CLASSROOM EXERCISES (32H). IN CLASSROOM EXERCISES, STUDENTS ARE ASSIGNED, DIVIDED BY WORKGROUPS, ONE OR MORE EXERCISES, OR PROJECTS TO BE DEVELOPED DURING THE EXERCISE. THE EXERCISES INCLUDE ALL THE CONTENTS COVERED BY THE TEACHING UP TO THAT TIME AND ARE INSTRUMENTAL IN THE ACQUISITION OF THE DESIGN AND IMPLEMENTATION SKILLS OF LOGICAL CIRCUITS STARTING FROM THE REQUIREMENTS.

Teaching Methods

TEACHING INCLUDES THEORETICAL LESSONS (40H) AND CLASSROOM EXERCISES (32H). IN CLASSROOM EXERCISES, STUDENTS ARE ASSIGNED, DIVIDED BY WORKGROUPS, ONE OR MORE EXERCISES, OR PROJECTS TO BE DEVELOPED DURING THE EXERCISE. THE EXERCISES INCLUDE ALL THE CONTENTS COVERED BY THE TEACHING UP TO THAT TIME AND ARE INSTRUMENTAL IN THE ACQUISITION OF THE DESIGN AND IMPLEMENTATION SKILLS OF LOGICAL CIRCUITS STARTING FROM THE REQUIREMENTS.

	Verification of learning
	THE EVALUATION OF THE ACHIEVEMENT OF THE GOALS IS CARRIED OUT THROUGH A MEDIUM-TERM WRITTEN TEST ON THE TOPICS CONCERNING BASIC CONCEPTS, THE BOOLEAN ALGEBRA AND THE COMBINATORIAL NETWORKS. IT IS ARTICULATED IN VARIOUS OPEN-ENDED QUESTIONS AIMED AT ASCERTAINING THE ABILITY TO DESIGN COMBINATORIAL CIRCUITS BY EVALUATING THEIR FUNCTIONAL CHARACTERISTICS, INCLUDING COMBINATORIAL CIRCUITS WITH PREDEFINED FUNCTIONALITY. THEN, THE STUDENT MUST PASS A FINAL WRITTEN TEST, ARTICULATED IN A PROJECT OF A SEQUENTIAL NETWORK USING VARIOUS TYPES OF FLIP-FLOPS, IMPLEMENTATIONS IN VHDL AND SOME METHODOLOGICAL QUESTIONS. THE ORAL EXAMINATION CONSISTS OF THE DISCUSSION OF THE FINAL DRAFT. EACH TEST CAN REACH A MAXIMUM SCORE EQUAL TO 30. THE FINAL GRADE IS GIVEN BY THE WEIGHTED AVERAGE OF THE INDIVIDUAL TESTS, WHERE THE WEIGHT OF THE MEDIUM-TERM TEST IS 40%, THAT OF THE FINAL TEST IS 40% AND THE FINAL DISCUSSION IS 20%.

Verification of learning

THE EVALUATION OF THE ACHIEVEMENT OF THE GOALS IS CARRIED OUT THROUGH A MEDIUM-TERM WRITTEN TEST ON THE TOPICS CONCERNING BASIC CONCEPTS, THE BOOLEAN ALGEBRA AND THE COMBINATORIAL NETWORKS. IT IS ARTICULATED IN VARIOUS OPEN-ENDED QUESTIONS AIMED AT ASCERTAINING THE ABILITY TO DESIGN COMBINATORIAL CIRCUITS BY EVALUATING THEIR FUNCTIONAL CHARACTERISTICS, INCLUDING COMBINATORIAL CIRCUITS WITH PREDEFINED FUNCTIONALITY. THEN, THE STUDENT MUST PASS A FINAL WRITTEN TEST, ARTICULATED IN A PROJECT OF A SEQUENTIAL NETWORK USING VARIOUS TYPES OF FLIP-FLOPS, IMPLEMENTATIONS IN VHDL AND SOME METHODOLOGICAL QUESTIONS. THE ORAL EXAMINATION CONSISTS OF THE DISCUSSION OF THE FINAL DRAFT. EACH TEST CAN REACH A MAXIMUM SCORE EQUAL TO 30. THE FINAL GRADE IS GIVEN BY THE WEIGHTED AVERAGE OF THE INDIVIDUAL TESTS, WHERE THE WEIGHT OF THE MEDIUM-TERM TEST IS 40%, THAT OF THE FINAL TEST IS 40% AND THE FINAL DISCUSSION IS 20%.

	Texts
	M. MORRIS MANO, CHARLES R. KIME: RETI LOGICHE, IV EDIZIONE, PEARSON - PRENTICE HALL, 2008 TEACHING MATERIALS.

	More Information
	THE TEACHING IS PROVIDED WITH MANDATORY ATTENDANCE. THE TEACHING LANGUAGE IS ITALIAN.

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Luca GRECO | Logic Networks