ROSALBA LIGUORI | DIGITAL ELECTRONICS

cod. 0612400031

DIGITAL ELECTRONICS

	0612400031
	DIPARTIMENTO DI INGEGNERIA INDUSTRIALE
	EQF6
	ELECTRONIC ENGINEERING
	2019/2020

PERCORSO COMUNE

	OBBLIGATORIO
	YEAR OF COURSE 2
	YEAR OF DIDACTIC SYSTEM 2018
	SECONDO SEMESTRE

TEACHING UNITS

	SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
	ING-INF/01	9	90	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS

PROFESSORS

	GIAN DOMENICO LICCIARDO T Curriculum
	ROSALBA LIGUORI Curriculum

	Objectives
	The course aims to equip students with the basic knowledge of Digital Electronics. The structure and operation of elementary logic doors are analyzed, both in MOS technology and in bipolar technology. To this end, the course provides a methodological part and an application. The methodological part is devoted to the study of the most important aspects of the operation of the circuits, through analytical models in order to obtain the most significant parameters of the digital logic. The application part is devoted to carrying out computer-assisted exercises in order to acquire basic knowledge of VHDL hardware description, circuit simulators, and CAD layouts. KNOWLEDGE AND UNDERSTANDING. Understanding the operation of logic circuits and models for estimating their performance. Knowledge of project methodologies of static CMOS logic. Knowledge of CAD tools for computer-aided design, synthesis and testing, of integrated circuits. APPLYING KNOWLEDGE AND UNDERSTANDING. To be able to analyze the operation of logic circuits. Being able to design a low and medium CMOS logic circuit with semi-custom and full-custom techniques. Know how to achieve low and medium complexity CMOS circuits layout. Being able to use tools to implement and test logic circuits. COMMUNICATION SKILLS. Know how to choose the logic family that best meets the specifications. Know how to approach simple logic functions. Know how to choose the most appropriate tools for creating an assigned project. LEARNING SKILLS. Know how to work together. Being able to expose a topic related to large-scale digital integration systems orally and in writing. Know how to relate in writing and oral about a project.

The course aims to equip students with the basic knowledge of Digital Electronics. The structure and operation of elementary logic doors are analyzed, both in MOS technology and in bipolar technology. To this end, the course provides a methodological part and an application. The methodological part is devoted to the study of the most important aspects of the operation of the circuits, through analytical models in order to obtain the most significant parameters of the digital logic. The application part is devoted to carrying out computer-assisted exercises in order to acquire basic knowledge of VHDL hardware description, circuit simulators, and CAD layouts.
KNOWLEDGE AND UNDERSTANDING.
Understanding the operation of logic circuits and models for estimating their performance. Knowledge of project methodologies of static CMOS logic. Knowledge of CAD tools for computer-aided design, synthesis and testing, of integrated circuits.

APPLYING KNOWLEDGE AND UNDERSTANDING.
To be able to analyze the operation of logic circuits. Being able to design a low and medium CMOS logic circuit with semi-custom and full-custom techniques. Know how to achieve low and medium complexity CMOS circuits layout. Being able to use tools to implement and test logic circuits.

COMMUNICATION SKILLS.
Know how to choose the logic family that best meets the specifications. Know how to approach simple logic functions. Know how to choose the most appropriate tools for creating an assigned project.

LEARNING SKILLS.
Know how to work together. Being able to expose a topic related to large-scale digital integration systems orally and in writing. Know how to relate in writing and oral about a project.

	Prerequisites
	PREREQUISITES ARE: -Knowledge of the foundations of electronics is required for the successful achievement of the goals set for the student.

	Contents
	GENERAL CHARACTERISTICS OF LOGIC FAMILIES (LECTURES: 4H; EXERCISE 0H) STATIC CHARACTERISTICS; DYNAMIC CHARACTERISTICS; FAN-IN, FAN-OUT, INTEGRATION LEVEL. LOGIC GATES IN BIPOLAR TECHNOLOGY (LECTURES: 10; EXERCISE 3) THE TTL LOGIC FAMILY, WIRED AND OPEN-COLLECTOR CIRCUITS. CML LOGIC FAMILY AND ECL, INTERFACE CIRCUITS. LOGIC GATES IN CMOS TECHNOLOGY (LECTURES: 10; EXERCISE 3) STATIC AND DYNAMIC PERFORMANCE OF NMOS LOGIC FAMILIES, MOS RESISTIVE LOAD CARRYING, EEMOS, EDMOS, LOGICAL EXPANSIONS, CMOS LOGIC PERFORMANCE. LOGIC DESIGN (LECTURES: 5; EXERCISE 0) BOOLEAN ALGEBRA; FULL-CUSTOM AND SEMI-CUSTOM PROJECT FLOW. TRUTH TABLES AND MINIMIZATION OF BINARY FUNCTIONS; COMPLEX CMOS LOGIC PORTS; TRANSMISSION PORTS. PHYSICAL DESIGN (LECTURES: 10; EXERCISE 4; LAB: 5) MOSFET SWITCH-LEVEL MODEL; PARASITE PARAMETERS; DELAY AND POWER DISSIPATION ESTIMATION OF A CMOS CIRCUIT. SEQUENTIAL CIRCUITS (LECTURES. 10; EXERCISE. 4: LAB 5) BISTABLE PRINCIPLE; LATCH, OPERATION; LATCH S-R; LATCH J-K, D-LATCH STATIC AND DYNAMIC. FLIP-FLOP MASTER-SLAVE TYPE D STATIC AND DYNAMIC; TRUE SINGLE PHASE OF CLOCK FLIP-FLOP. TIME OF SET-UP, HOLD, TCQ E TDQ. OVERLAP BETWEEN CLOCK PHASES. FSM (ORE LEZ. 4; ORE ESERC. 3: ORE LAB 0) GENERAL STRUCTURE OF A FSM; CONSTRAINS GENERATED BY HOLD AND SET-UP TIME; APPLICATIONS. DESIGN AND SIMULATION OF CMOS LAYOUT (LAECTURES 5; EXERCISE 0: LAB 5) INTRODUCTION TO THE CMOS FABRICATION PROCESS; DESIGN RULES; LAYOUT EDITOR; DESIGN-RULE CHECKER; STANDARD CELLS; TRANSISTOR CHAINING AND INTEGRATION TECHNIQUES. APPLICATIONS. SPICE; INPUT FILE; MAIN COMMANDS; SPICE MODELS OF MOSFET AND BJT. APPLICATIONS.

Contents

GENERAL CHARACTERISTICS OF LOGIC FAMILIES (LECTURES: 4H; EXERCISE 0H)
STATIC CHARACTERISTICS; DYNAMIC CHARACTERISTICS; FAN-IN, FAN-OUT, INTEGRATION LEVEL.

LOGIC GATES IN BIPOLAR TECHNOLOGY (LECTURES: 10; EXERCISE 3)
THE TTL LOGIC FAMILY, WIRED AND OPEN-COLLECTOR CIRCUITS. CML LOGIC FAMILY AND ECL, INTERFACE CIRCUITS.

LOGIC GATES IN CMOS TECHNOLOGY (LECTURES: 10; EXERCISE 3)
STATIC AND DYNAMIC PERFORMANCE OF NMOS LOGIC FAMILIES, MOS RESISTIVE LOAD CARRYING, EEMOS, EDMOS, LOGICAL EXPANSIONS, CMOS LOGIC PERFORMANCE.

LOGIC DESIGN (LECTURES: 5; EXERCISE 0)
BOOLEAN ALGEBRA; FULL-CUSTOM AND SEMI-CUSTOM PROJECT FLOW. TRUTH TABLES AND MINIMIZATION OF BINARY FUNCTIONS; COMPLEX CMOS LOGIC PORTS; TRANSMISSION PORTS.

PHYSICAL DESIGN (LECTURES: 10; EXERCISE 4; LAB: 5)
MOSFET SWITCH-LEVEL MODEL; PARASITE PARAMETERS; DELAY AND POWER DISSIPATION ESTIMATION OF A CMOS CIRCUIT.

SEQUENTIAL CIRCUITS (LECTURES. 10; EXERCISE. 4: LAB 5)
BISTABLE PRINCIPLE; LATCH, OPERATION; LATCH S-R; LATCH J-K, D-LATCH STATIC AND DYNAMIC. FLIP-FLOP MASTER-SLAVE TYPE D STATIC AND DYNAMIC; TRUE SINGLE PHASE OF CLOCK FLIP-FLOP. TIME OF SET-UP, HOLD, TCQ E TDQ.
OVERLAP BETWEEN CLOCK PHASES.

FSM (ORE LEZ. 4; ORE ESERC. 3: ORE LAB 0)
GENERAL STRUCTURE OF A FSM; CONSTRAINS GENERATED BY HOLD AND SET-UP TIME; APPLICATIONS.

DESIGN AND SIMULATION OF CMOS LAYOUT (LAECTURES 5; EXERCISE 0: LAB 5)
INTRODUCTION TO THE CMOS FABRICATION PROCESS; DESIGN RULES; LAYOUT EDITOR; DESIGN-RULE CHECKER; STANDARD CELLS; TRANSISTOR CHAINING AND INTEGRATION TECHNIQUES. APPLICATIONS.
SPICE; INPUT FILE; MAIN COMMANDS; SPICE MODELS OF MOSFET AND BJT. APPLICATIONS.

	Teaching Methods
	TEACHING INVOLVES THE PROVISION OF THEORETICAL LESSONS AND LABORATORY EXERCISES IN A NUMBER OF HOURS REPORTED IN THE COURSE CONTENT. THE EXERCISES INVOLVE THE VARIOUS ISSUES ADDRESSED IN THE THEORETICAL LESSONS AND ARE STRUCTURED SO AS TO FACILITATE THE LEARNING OF TECHNIQUES AND METHODS FOR SOLVING BASIC PROBLEMS OF DIGITAL ANALYSIS AND SYNTHESIS AND THE DESIGN OF THE LAYOUT OF CMOS CIRCUITS BY MEANS OF CAD TOOLS.

Teaching Methods

TEACHING INVOLVES THE PROVISION OF THEORETICAL LESSONS AND LABORATORY EXERCISES IN A NUMBER OF HOURS REPORTED IN THE COURSE CONTENT. THE EXERCISES INVOLVE THE VARIOUS ISSUES ADDRESSED IN THE THEORETICAL LESSONS AND ARE STRUCTURED SO AS TO FACILITATE THE LEARNING OF TECHNIQUES AND METHODS FOR SOLVING BASIC PROBLEMS OF DIGITAL ANALYSIS AND SYNTHESIS AND THE DESIGN OF THE LAYOUT OF CMOS CIRCUITS BY MEANS OF CAD TOOLS.

	Verification of learning
	THE EVALUATION OF THE COURSE WILL BE EXPRESSED IN THIRTIETH (THE MINIMUM LEVEL CORRESPOND TO "18" AND THE MAXIMUM TO "30 AND LODE"). IT WILL THROUGH TWO WRITE TESTS OF VERIFICATION TO BE DONE DURING THE LESSONS, WHICH EXEMPT THE STUDENT FROM THE ORAL TEST. THE TESTS WILL CONSIST OF NUMERICAL EXERCISES AND THEORETICAL QUESTIONS ON THE TOPICS COVERED IN THE COURSE IN THE LESSONS BEFORE THE TEST. THEY WANT: 1) VERIFY THE LEARNING OF THE TOPICS TREATED IN THE THEORY HOURS; 2) VERIFY THE EXPOSURE CAPACITY OF THE TOPICS CONTAINED; 4) VERIFY THE JUDGMENT AUTONOMY IN PROPOSING THE MOST APPROPRIATE APPROACH TO ARGUMENT AS REQUIRED. AT THE END OF THE SECOND TEST, IF ALL ARE SUFFICIENT, THE ARITHMETIC AVERAGE OF RESULTS WILL GENERATE A STARTING VOTE. THIS MAY BE ACCEPTED BY THE STUDENT OR IMPROVED AT THE REQUEST OF THE STUDENT THROUGH AN ORAL TEST OF ABOUT 30 MINUTES WITH QUESTIONS ABOUT THE ENTIRE PROGRAM. IF ONE OF THE TESTS HAS TO BE UNDER SUFFICIENCY, THE STUDENT MUST NECESSARILY SUPPORT AN ORAL VERIFICATION IN WHICH HE WILL HAVE TO DEMONSTRATE TO HAVE OVERCOME THE DIFFICULTIES OF THE WRITTEN TEST. THE ACHIEVEMENT OF SUFFICIENCY REQUIRES THAT THE STUDENT IS ABLE TO KNOW, RECOGNIZE AND ANALYZE THE BASIC OPERATION OF THE LOGICAL PORTS PRESENTED IN THE COURSE AND TO KNOW THE BASIC CONCEPTS OF EVERY MACRO-TOPIC CARRIED OUT IN LESSONS. THE ACHIEVEMENT OF EXCELLENCE IS ACHIEVED THROUGH AN ORAL TEST THAT FOLLOWS TWO WRITTEN TESTS ASSESSED WITH AN ARITHMETIC AVERAGE OF 28/30, IN WHICH THE STUDENT SHOWS THAT HE HAS REACHED A HIGH LEVEL OF AUTONOMY IN THE ANALYSIS OF CIRCUITS PROPOSED EVEN IF THEY ARE NEW WITH RESPECT TO THOSE SHOWED IN THE LESSON.

Verification of learning

THE EVALUATION OF THE COURSE WILL BE EXPRESSED IN THIRTIETH (THE MINIMUM LEVEL CORRESPOND TO "18" AND THE MAXIMUM TO "30 AND LODE"). IT WILL THROUGH TWO WRITE TESTS OF VERIFICATION TO BE DONE DURING THE LESSONS, WHICH EXEMPT THE STUDENT FROM THE ORAL TEST. THE TESTS WILL CONSIST OF NUMERICAL EXERCISES AND THEORETICAL QUESTIONS ON THE TOPICS COVERED IN THE COURSE IN THE LESSONS BEFORE THE TEST. THEY WANT: 1) VERIFY THE LEARNING OF THE TOPICS TREATED IN THE THEORY HOURS; 2) VERIFY THE EXPOSURE CAPACITY OF THE TOPICS CONTAINED; 4) VERIFY THE JUDGMENT AUTONOMY IN PROPOSING THE MOST APPROPRIATE APPROACH TO ARGUMENT AS REQUIRED.
AT THE END OF THE SECOND TEST, IF ALL ARE SUFFICIENT, THE ARITHMETIC AVERAGE OF RESULTS WILL GENERATE A STARTING VOTE. THIS MAY BE ACCEPTED BY THE STUDENT OR IMPROVED AT THE REQUEST OF THE STUDENT THROUGH AN ORAL TEST OF ABOUT 30 MINUTES WITH QUESTIONS ABOUT THE ENTIRE PROGRAM. IF ONE OF THE TESTS HAS TO BE UNDER SUFFICIENCY, THE STUDENT MUST NECESSARILY SUPPORT AN ORAL VERIFICATION IN WHICH HE WILL HAVE TO DEMONSTRATE TO HAVE OVERCOME THE DIFFICULTIES OF THE WRITTEN TEST. THE ACHIEVEMENT OF SUFFICIENCY REQUIRES THAT THE STUDENT IS ABLE TO KNOW, RECOGNIZE AND ANALYZE THE BASIC OPERATION OF THE LOGICAL PORTS PRESENTED IN THE COURSE AND TO KNOW THE BASIC CONCEPTS OF EVERY MACRO-TOPIC CARRIED OUT IN LESSONS. THE ACHIEVEMENT OF EXCELLENCE IS ACHIEVED THROUGH AN ORAL TEST THAT FOLLOWS TWO WRITTEN TESTS ASSESSED WITH AN ARITHMETIC AVERAGE OF 28/30, IN WHICH THE STUDENT SHOWS THAT HE HAS REACHED A HIGH LEVEL OF AUTONOMY IN THE ANALYSIS OF CIRCUITS PROPOSED EVEN IF THEY ARE NEW WITH RESPECT TO THOSE SHOWED IN THE LESSON.

	Texts
	J. P. UYEMURA, “CMOS LOGIC CIRCUITS DESIGN”, KLUWER ACADEMIC PRESS. J. M. RABAEY, A. CHANDRAKASAN, B. NIKOLIC: "CIRCUITI INTEGRATI DIGITALI; L'OTTICA DEL PROGETTISTA." PARSON - PRENTICE HALL. B. RICCÒ, F. FANTINI, P. BRAMBILLA: “INTRODUZIONE AI CIRCUITI INTEGRATI DIGITALI”, ZANICHELLI TELETTRA. LECTURE NOTES

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ROSALBA LIGUORI | DIGITAL ELECTRONICS