ROSALBA LIGUORI | DIGITAL ELECTRONICS

cod. 0612400031

DIGITAL ELECTRONICS

	0612400031
	DEPARTMENT OF INDUSTRIAL ENGINEERING
	EQF6
	ELECTRONIC ENGINEERING
	2024/2025

PERCORSO IN COMMON

	OBBLIGATORIO
	YEAR OF COURSE 2
	YEAR OF DIDACTIC SYSTEM 2018
	SPRING SEMESTER

TEACHING UNITS

	SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
	ING-INF/01	9	90	LESSONS	COMPULSORY SUBJECTS, CHARACTERISTIC OF THE CLASS

PROFESSORS

	GIAN DOMENICO LICCIARDO T Curriculum
	ROSALBA LIGUORI Curriculum

	Objectives
	THE COURSE AIMS TO EQUIP STUDENTS WITH THE BASIC KNOWLEDGE OF DIGITAL ELECTRONICS. THE STRUCTURE AND OPERATION OF ELEMENTARY LOGIC DOORS ARE ANALYZED, BOTH IN MOS TECHNOLOGY AND IN BIPOLAR TECHNOLOGY. TO THIS END, THE COURSE PROVIDES A METHODOLOGICAL PART AND AN APPLICATION. THE METHODOLOGICAL PART IS DEVOTED TO THE STUDY OF THE MOST IMPORTANT ASPECTS OF THE OPERATION OF THE CIRCUITS, THROUGH ANALYTICAL MODELS IN ORDER TO OBTAIN THE MOST SIGNIFICANT PARAMETERS OF THE DIGITAL LOGIC. THE APPLICATION PART IS DEVOTED TO CARRYING OUT COMPUTER-ASSISTED EXERCISES IN ORDER TO ACQUIRE BASIC KNOWLEDGE OF THE SPICE CIRCUIT SIMULATORS AND LAYOUT EDITORS. KNOWLEDGE AND UNDERSTANDING. UNDERSTANDING THE OPERATION OF LOGIC CIRCUITS AND MODELS FOR ESTIMATING THEIR PERFORMANCE. KNOWLEDGE OF PROJECT METHODOLOGIES OF STATIC CMOS LOGIC. KNOWLEDGE OF CAD TOOLS FOR COMPUTER-AIDED DESIGN, SYNTHESIS AND TESTING, OF INTEGRATED CIRCUITS. APPLYING KNOWLEDGE AND UNDERSTANDING. TO BE ABLE TO ANALYZE THE OPERATION OF LOGIC CIRCUITS. BEING ABLE TO DESIGN A LOW AND MEDIUM CMOS LOGIC CIRCUIT WITH SEMI-CUSTOM AND FULL-CUSTOM TECHNIQUES. KNOW HOW TO ACHIEVE LOW AND MEDIUM COMPLEXITY CMOS CIRCUITS LAYOUT. BEING ABLE TO USE TOOLS TO IMPLEMENT AND TEST LOGIC CIRCUITS. COMMUNICATION SKILLS. KNOW HOW TO CHOOSE THE LOGIC FAMILY THAT BEST MEETS THE SPECIFICATIONS. KNOW HOW TO APPROACH SIMPLE LOGIC FUNCTIONS. KNOW HOW TO CHOOSE THE MOST APPROPRIATE TOOLS FOR CREATING AN ASSIGNED PROJECT. LEARNING SKILLS. KNOW HOW TO WORK TOGETHER. BEING ABLE TO EXPOSE A TOPIC RELATED TO LARGE-SCALE DIGITAL INTEGRATION SYSTEMS ORALLY AND IN WRITING. KNOW HOW TO RELATE IN WRITING AND ORAL ABOUT A PROJECT.

THE COURSE AIMS TO EQUIP STUDENTS WITH THE BASIC KNOWLEDGE OF DIGITAL ELECTRONICS. THE STRUCTURE AND OPERATION OF ELEMENTARY LOGIC DOORS ARE ANALYZED, BOTH IN MOS TECHNOLOGY AND IN BIPOLAR TECHNOLOGY. TO THIS END, THE COURSE PROVIDES A METHODOLOGICAL PART AND AN APPLICATION. THE METHODOLOGICAL PART IS DEVOTED TO THE STUDY OF THE MOST IMPORTANT ASPECTS OF THE OPERATION OF THE CIRCUITS, THROUGH ANALYTICAL MODELS IN ORDER TO OBTAIN THE MOST SIGNIFICANT PARAMETERS OF THE DIGITAL LOGIC. THE APPLICATION PART IS DEVOTED TO CARRYING OUT COMPUTER-ASSISTED EXERCISES IN ORDER TO ACQUIRE BASIC KNOWLEDGE OF THE SPICE CIRCUIT SIMULATORS AND LAYOUT EDITORS.

KNOWLEDGE AND UNDERSTANDING.
UNDERSTANDING THE OPERATION OF LOGIC CIRCUITS AND MODELS FOR ESTIMATING THEIR PERFORMANCE. KNOWLEDGE OF PROJECT METHODOLOGIES OF STATIC CMOS LOGIC. KNOWLEDGE OF CAD TOOLS FOR COMPUTER-AIDED DESIGN, SYNTHESIS AND TESTING, OF INTEGRATED CIRCUITS.

APPLYING KNOWLEDGE AND UNDERSTANDING.
TO BE ABLE TO ANALYZE THE OPERATION OF LOGIC CIRCUITS. BEING ABLE TO DESIGN A LOW AND MEDIUM CMOS LOGIC CIRCUIT WITH SEMI-CUSTOM AND FULL-CUSTOM TECHNIQUES. KNOW HOW TO ACHIEVE LOW AND MEDIUM COMPLEXITY CMOS CIRCUITS LAYOUT. BEING ABLE TO USE TOOLS TO IMPLEMENT AND TEST LOGIC CIRCUITS.

COMMUNICATION SKILLS.
KNOW HOW TO CHOOSE THE LOGIC FAMILY THAT BEST MEETS THE SPECIFICATIONS. KNOW HOW TO APPROACH SIMPLE LOGIC FUNCTIONS. KNOW HOW TO CHOOSE THE MOST APPROPRIATE TOOLS FOR CREATING AN ASSIGNED PROJECT.

LEARNING SKILLS.
KNOW HOW TO WORK TOGETHER. BEING ABLE TO EXPOSE A TOPIC RELATED TO LARGE-SCALE DIGITAL INTEGRATION SYSTEMS ORALLY AND IN WRITING. KNOW HOW TO RELATE IN WRITING AND ORAL ABOUT A PROJECT.

	Prerequisites
	PREREQUISITES ARE: -KNOWLEDGE OF THE FOUNDATIONS OF ELECTRONICS IS REQUIRED FOR THE SUCCESSFUL ACHIEVEMENT OF THE GOALS SET FOR THE STUDENT.

	Contents
	INTRODUCTORY CONCEPTS TO DIGITAL ELECTRONICS (LESSONS 6 HOURS; PRACTICE HOURS 0) • DEFINITION OF DIGITAL ELECTRONICS, DIGITAL SIGNALS AND LOGICAL ABSTRACTION LEVELS. • GENERAL CHARACTERISTICS OF DIGITAL CIRCUITS: NOISE IMMUNITY, SIGNAL REGENERATION, • SPICE MODEL OF THE MOSFET • CONSTANT FIELD AND CONSTANT VOLTAGE SCALING; INTEGRATION CONCEPT. • STATIC CHARACTERISTICS; DYNAMIC CHARACTERISTICS; FAN IN, FAN OUT. LOGIC GATES IN NMOS TECHNOLOGY (LESSON HOURS 3; PRACTICE HOURS 0) • NMOS LOGIC PORT WITH RESISTIVE LOAD; • LAYER RESISTANCE AND BUILT-IN RESISTOR. LOGIC GATES IN CMOS TECHNOLOGY (LESSONS 15 HOURS; PRACTICE HOURS 12) • FCMOS LOGIC: STATIC CHARACTERISTICS (VTC, NOISE MARGINS, LOGIC THRESHOLD). O LEAKAGE CURRENTS AND STATIC POWER LOSS O DYNAMIC CHARACTERISTICS: SWITCHING TIME AND PROPAGATION DELAY O DYNAMIC POWER DISSIPATION • PSEUDO-NMOS LOGIC GATES; O CVS LOGIC • PASS-TRANSISTOR LOGIC GATES (PTLE COMPLEMENTARY PTL): O SHANNON EXPANSION, O PASS-TRANSISTOR AND TRANSMISSION GATES. OR MULTIPLEXERS LOGICAL AND PHYSICAL DESIGN (LESSONS 6 HOURS; PRACTICE HOURS 8; LAB HOURS 5) • OVERVIEW OF FULL-CUSTOM AND SEMI-CUSTOM PROJECT FLOW; • COMPLEX CMOS LOGIC GATES. • PARASITIC PARAMETERS; ESTIMATION OF THE DELAYS AND OF THE DISSIPATED POWER OF A CMOS CIRCUIT. SEQUENTIAL CIRCUITS (LESSONS 15 HOURS; PRACTICE HOURS 4: LAB HOURS 5) • BISTABLE OPERATING PRINCIPLE; • LATCH, OPERATING PRINCIPLE; S-R LATCH, SYNCHRONOUS S-R LATCH; J-K LATCH, STATIC AND DYNAMIC D-LATCH. • STATIC AND DYNAMIC D-TYPE MASTER-SLAVE FLIP-FLOP; TRUE SINGLE PHASE OF CLOCK FLIP-FLOP. CALCULATION OF SET-UP, HOLD, TCQ AND TDQ TIMES. • OVERLAP PROBLEMS BETWEEN CLOCK PHASES. LAYOUT CREATION AND SIMULATION (LESSONS 6 HOURS; PRACTICE HOURS 0: LAB HOURS 5) • INTRODUCTION TO THE CMOS MANUFACTURING PROCESS; • DESIGN RULES; • USE OF A LAYOUT EDITOR; • TRANSISTOR CHAINING AND INTEGRATION TECHNIQUES.

Contents

INTRODUCTORY CONCEPTS TO DIGITAL ELECTRONICS (LESSONS 6 HOURS; PRACTICE HOURS 0)
• DEFINITION OF DIGITAL ELECTRONICS, DIGITAL SIGNALS AND LOGICAL ABSTRACTION LEVELS.
• GENERAL CHARACTERISTICS OF DIGITAL CIRCUITS: NOISE IMMUNITY, SIGNAL REGENERATION,
• SPICE MODEL OF THE MOSFET
• CONSTANT FIELD AND CONSTANT VOLTAGE SCALING; INTEGRATION CONCEPT.
• STATIC CHARACTERISTICS; DYNAMIC CHARACTERISTICS; FAN IN, FAN OUT.

LOGIC GATES IN NMOS TECHNOLOGY (LESSON HOURS 3; PRACTICE HOURS 0)
• NMOS LOGIC PORT WITH RESISTIVE LOAD;
• LAYER RESISTANCE AND BUILT-IN RESISTOR.
LOGIC GATES IN CMOS TECHNOLOGY (LESSONS 15 HOURS; PRACTICE HOURS 12)
• FCMOS LOGIC: STATIC CHARACTERISTICS (VTC, NOISE MARGINS, LOGIC THRESHOLD).
O LEAKAGE CURRENTS AND STATIC POWER LOSS
O DYNAMIC CHARACTERISTICS: SWITCHING TIME AND PROPAGATION DELAY
O DYNAMIC POWER DISSIPATION
• PSEUDO-NMOS LOGIC GATES;
O CVS LOGIC
• PASS-TRANSISTOR LOGIC GATES (PTLE COMPLEMENTARY PTL):
O SHANNON EXPANSION,
O PASS-TRANSISTOR AND TRANSMISSION GATES.
OR MULTIPLEXERS

LOGICAL AND PHYSICAL DESIGN (LESSONS 6 HOURS; PRACTICE HOURS 8; LAB HOURS 5)
• OVERVIEW OF FULL-CUSTOM AND SEMI-CUSTOM PROJECT FLOW;
• COMPLEX CMOS LOGIC GATES.
• PARASITIC PARAMETERS; ESTIMATION OF THE DELAYS AND OF THE DISSIPATED POWER OF A CMOS CIRCUIT.

SEQUENTIAL CIRCUITS (LESSONS 15 HOURS; PRACTICE HOURS 4: LAB HOURS 5)
• BISTABLE OPERATING PRINCIPLE;
• LATCH, OPERATING PRINCIPLE; S-R LATCH, SYNCHRONOUS S-R LATCH; J-K LATCH, STATIC AND DYNAMIC D-LATCH.
• STATIC AND DYNAMIC D-TYPE MASTER-SLAVE FLIP-FLOP; TRUE SINGLE PHASE OF CLOCK FLIP-FLOP. CALCULATION OF SET-UP, HOLD, TCQ AND TDQ TIMES.
• OVERLAP PROBLEMS BETWEEN CLOCK PHASES.

LAYOUT CREATION AND SIMULATION (LESSONS 6 HOURS; PRACTICE HOURS 0: LAB HOURS 5)
• INTRODUCTION TO THE CMOS MANUFACTURING PROCESS;
• DESIGN RULES;
• USE OF A LAYOUT EDITOR;
• TRANSISTOR CHAINING AND INTEGRATION TECHNIQUES.

	Teaching Methods
	TEACHING INVOLVES THE PROVISION OF THEORETICAL LESSONS AND LABORATORY EXERCISES IN A NUMBER OF HOURS REPORTED IN THE COURSE CONTENT. THE EXERCISES INVOLVE THE VARIOUS ISSUES ADDRESSED IN THE THEORETICAL LESSONS AND ARE STRUCTURED SO AS TO FACILITATE THE LEARNING OF TECHNIQUES AND METHODS FOR SOLVING BASIC PROBLEMS OF DIGITAL ANALYSIS AND SYNTHESIS AND THE DESIGN OF THE LAYOUT OF CMOS CIRCUITS BY MEANS OF CAD TOOLS.

Teaching Methods

TEACHING INVOLVES THE PROVISION OF THEORETICAL LESSONS AND LABORATORY EXERCISES IN A NUMBER OF HOURS REPORTED IN THE COURSE CONTENT. THE EXERCISES INVOLVE THE VARIOUS ISSUES ADDRESSED IN THE THEORETICAL LESSONS AND ARE STRUCTURED SO AS TO FACILITATE THE LEARNING OF TECHNIQUES AND METHODS FOR SOLVING BASIC PROBLEMS OF DIGITAL ANALYSIS AND SYNTHESIS AND THE DESIGN OF THE LAYOUT OF CMOS CIRCUITS BY MEANS OF CAD TOOLS.

	Verification of learning
	THE EVALUATION OF THE COURSE WILL BE EXPRESSED IN THIRTIETH (THE MINIMUM LEVEL CORRESPOND TO "18" AND THE MAXIMUM TO "30 AND LODE"). IT WILL THROUGH TWO WRITE TESTS OF VERIFICATION TO BE DONE DURING THE LESSONS, AND AN ORAL TEST. THE TESTS WILL CONSIST OF NUMERICAL EXERCISES AND THEORETICAL QUESTIONS ON THE TOPICS COVERED IN THE COURSE IN THE LESSONS BEFORE THE TEST. THEY WANT: 1) VERIFY THE LEARNING OF THE TOPICS TREATED IN THE THEORY HOURS; 2) VERIFY THE EXPOSURE CAPACITY OF THE TOPICS CONTAINED; 4) VERIFY THE JUDGMENT AUTONOMY IN PROPOSING THE MOST APPROPRIATE APPROACH TO ARGUMENT AS REQUIRED. AT THE END OF THE SECOND TEST, IF ALL ARE SUFFICIENT, THE ARITHMETIC AVERAGE OF RESULTS WILL GENERATE A STARTING VOTE, WHICH WILL BE INTEGRATED BY THE ORAL TEST OF ABOUT 30 MINUTES WITH QUESTIONS ABOUT THE ENTIRE PROGRAM. IF ONE OF THE TESTS HAS TO BE UNDER SUFFICIENCY, THE STUDENT MUST NECESSARILY SUPPORT AN ORAL VERIFICATION IN WHICH HE WILL HAVE TO DEMONSTRATE TO HAVE OVERCOME THE DIFFICULTIES OF THE WRITTEN TEST. THE ACHIEVEMENT OF SUFFICIENCY REQUIRES THAT THE STUDENT IS ABLE TO KNOW, RECOGNIZE AND ANALYZE THE BASIC OPERATION OF THE LOGICAL PORTS PRESENTED IN THE COURSE AND TO KNOW THE BASIC CONCEPTS OF EVERY MACRO-TOPIC CARRIED OUT IN LESSONS. THE ACHIEVEMENT OF EXCELLENCE IS ACHIEVED THROUGH AN ORAL TEST THAT FOLLOWS TWO WRITTEN TESTS ASSESSED WITH AN ARITHMETIC AVERAGE OF 28/30, IN WHICH THE STUDENT SHOWS THAT HE HAS REACHED A HIGH LEVEL OF AUTONOMY IN THE ANALYSIS OF CIRCUITS PROPOSED EVEN IF THEY ARE NEW WITH RESPECT TO THOSE SHOWED IN THE LESSON.

Verification of learning

THE EVALUATION OF THE COURSE WILL BE EXPRESSED IN THIRTIETH (THE MINIMUM LEVEL CORRESPOND TO "18" AND THE MAXIMUM TO "30 AND LODE"). IT WILL THROUGH TWO WRITE TESTS OF VERIFICATION TO BE DONE DURING THE LESSONS, AND AN ORAL TEST. THE TESTS WILL CONSIST OF NUMERICAL EXERCISES AND THEORETICAL QUESTIONS ON THE TOPICS COVERED IN THE COURSE IN THE LESSONS BEFORE THE TEST. THEY WANT: 1) VERIFY THE LEARNING OF THE TOPICS TREATED IN THE THEORY HOURS; 2) VERIFY THE EXPOSURE CAPACITY OF THE TOPICS CONTAINED; 4) VERIFY THE JUDGMENT AUTONOMY IN PROPOSING THE MOST APPROPRIATE APPROACH TO ARGUMENT AS REQUIRED.
AT THE END OF THE SECOND TEST, IF ALL ARE SUFFICIENT, THE ARITHMETIC AVERAGE OF RESULTS WILL GENERATE A STARTING VOTE, WHICH WILL BE INTEGRATED BY THE ORAL TEST OF ABOUT 30 MINUTES WITH QUESTIONS ABOUT THE ENTIRE PROGRAM. IF ONE OF THE TESTS HAS TO BE UNDER SUFFICIENCY, THE STUDENT MUST NECESSARILY SUPPORT AN ORAL VERIFICATION IN WHICH HE WILL HAVE TO DEMONSTRATE TO HAVE OVERCOME THE DIFFICULTIES OF THE WRITTEN TEST. THE ACHIEVEMENT OF SUFFICIENCY REQUIRES THAT THE STUDENT IS ABLE TO KNOW, RECOGNIZE AND ANALYZE THE BASIC OPERATION OF THE LOGICAL PORTS PRESENTED IN THE COURSE AND TO KNOW THE BASIC CONCEPTS OF EVERY MACRO-TOPIC CARRIED OUT IN LESSONS. THE ACHIEVEMENT OF EXCELLENCE IS ACHIEVED THROUGH AN ORAL TEST THAT FOLLOWS TWO WRITTEN TESTS ASSESSED WITH AN ARITHMETIC AVERAGE OF 28/30, IN WHICH THE STUDENT SHOWS THAT HE HAS REACHED A HIGH LEVEL OF AUTONOMY IN THE ANALYSIS OF CIRCUITS PROPOSED EVEN IF THEY ARE NEW WITH RESPECT TO THOSE SHOWED IN THE LESSON.

	Texts
	J. P. UYEMURA, “CMOS LOGIC CIRCUITS DESIGN”, KLUWER ACADEMIC PRESS. J. M. RABAEY, A. CHANDRAKASAN, B. NIKOLIC: "CIRCUITI INTEGRATI DIGITALI; L'OTTICA DEL PROGETTISTA." PARSON - PRENTICE HALL. MANUALS OF THE TOOLS, SLIDES AND ADDITIONAL MATERIAL WILL BE PROVIDED DURING THE COURSE.

	More Information
	THE COURSE IS HELD IN ITALIAN LANGUAGE.

Lessons Timetable

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ROSALBA LIGUORI | DIGITAL ELECTRONICS