Ugo FIORE | COMPUTER ARCHITECTURE

cod. 0512100002

COMPUTER ARCHITECTURE

	0512100002
	COMPUTER SCIENCE
	EQF6
	COMPUTER SCIENCE
	2024/2025

PERCORSO COMUNE

	OBBLIGATORIO
	YEAR OF COURSE 1
	YEAR OF DIDACTIC SYSTEM 2017
	AUTUMN SEMESTER

TEACHING UNITS

SSD	CFU	HOURS	ACTIVITY	TYPE OF ACTIVITY
INF/01	7	56	LESSONS	BASIC COMPULSORY SUBJECTS
INF/01	2	16	EXERCISES	BASIC COMPULSORY SUBJECTS

PROFESSORS

	ARCANGELO CASTIGLIONE T Curriculum
	UGO FIORE Curriculum

	Objectives
	Objective The educational goal of the course is to allow the student to learn the fundamental elements of the architecture of a modern computing system, with particular emphasis on the MIPS processor. Knowledge and understanding The main knowledge achieved by the student at the end of the course will include, more specifically: -Representation of information (instructions and data). -Computer arithmetic (arithmetic for integers, floating point, two's complement). -Boolean Algebra and combinational networks. -Combinational modules and storage elements. -Design of the Arithmetic-Logic Unit (ALU). -MIPS processor assembly language. -Design of the data processing unit in the single-cycle MIPS processor. -Design of the control unit in the single-cycle MIPS processor. -Using the pipelining technique to improve MIPS processor performance. -Memory hierarchy. Applying knowledge and understanding At the end of the course, the student will be able to: -Convert integer or floating point numbers between different bases in weighted positional systems. -Represent numbers and characters in different representation systems. -Design and analyze simple combinational networks. -Use standard combinational modules to build combinational networks. -Program in assembly language (MIPS Instruction Set Architecture). -Design the processing and control units for the single-cycle MIPS microprocessor. -Optimize the performance of the MIPS microprocessor using the pipelining technique. -Recognize the presence of hazards given in Assembler code fragments. -Understand how the memory hierarchy works. Autonomy of judgement The student will be able to compare and evaluate the quality of different solutions relating to the request to design a computing system. Communication skills The student will be able to: -Communicate, both in written and oral form, with specialist and non-specialist interlocutors concepts regarding a computing system's design, implementation, and evaluation. -Represent and communicate the results obtained following his professional activity through texts or virtual tools. Learning ability The student will be able to: -Acquire an effective study methodology that allows continuous and independent professional updating in relation to changing market needs. -Consult information online on topics relating to computer architecture.

Objective

The educational goal of the course is to allow the student to learn the fundamental elements of the architecture of a modern computing system, with particular emphasis on the MIPS processor.

Knowledge and understanding

The main knowledge achieved by the student at the end of the course will include, more specifically:
-Representation of information (instructions and data).
-Computer arithmetic (arithmetic for integers, floating point, two's complement).
-Boolean Algebra and combinational networks.
-Combinational modules and storage elements.
-Design of the Arithmetic-Logic Unit (ALU).
-MIPS processor assembly language.
-Design of the data processing unit in the single-cycle MIPS processor.
-Design of the control unit in the single-cycle MIPS processor.
-Using the pipelining technique to improve MIPS processor performance.
-Memory hierarchy.

Applying knowledge and understanding

At the end of the course, the student will be able to:
-Convert integer or floating point numbers between different bases in weighted positional systems.
-Represent numbers and characters in different representation systems.
-Design and analyze simple combinational networks.
-Use standard combinational modules to build combinational networks.
-Program in assembly language (MIPS Instruction Set Architecture).
-Design the processing and control units for the single-cycle MIPS microprocessor.
-Optimize the performance of the MIPS microprocessor using the pipelining technique.
-Recognize the presence of hazards given in Assembler code fragments.
-Understand how the memory hierarchy works.

Autonomy of judgement

The student will be able to compare and evaluate the quality of different solutions relating to the request to design a computing system.

Communication skills

The student will be able to:
-Communicate, both in written and oral form, with specialist and non-specialist interlocutors concepts regarding a computing system's design, implementation, and evaluation.
-Represent and communicate the results obtained following his professional activity through texts or virtual tools.

Learning ability

The student will be able to:
-Acquire an effective study methodology that allows continuous and independent professional updating in relation to changing market needs.
-Consult information online on topics relating to computer architecture.

	Prerequisites
	THE STUDENT MUST NOT HAVE SPECIAL COMPUTER KNOWLEDGE. A GOOD KNOWLEDGE AS A PERSONAL COMPUTER USER CAN HELP IN THE FRAMEWORK OF SOME PARTS OF THE COURSE. KNOWLEDGE (EVEN APPROXIMATE) OF PROGRAMMING CAN HELP IN THE PART RELATING TO ASSEMBLER PROGRAMMING.

	Contents
	1) COMPUTER ARCHITECTURE (1 CREDIT) 2) REPRESENTATION OF THE INFORMATION (1 CREDIT) 3) DIGITAL LOGIC (1 CREDIT) 4) ASSEMBLER LANGUAGE OF A RISC MACHINE (2 CREDITS) 5) IMPLEMENTATION OF THE SINGLE CYCLE PROCESSING UNIT (1 CREDIT) 6) PERFORMANCE MEASUREMENT, PERFORMANCE IMPROVEMENT THROUGH PIPELINES (2 CREDITS) 7) MEMORY HIERARCHIES (1 CREDIT)

	Teaching Methods
	THE COURSE CONSISTS OF LECTURES FOR 7 CFU AND TUTORIAL LESSONS FOR 2 CFU.

	Verification of learning
	WRITTEN TEST AND ORAL EXAMINATION. THERE ARE TWO IN ITINERE TESTS THAT EXEMPT THE WRITTEN TEST. THE WRITTEN TEST AND THE IN ITINERE TESTS ARE USED TO ASSESS THE STUDENT'S ABILITY TO PRACTICE THE NOTIONS OF TEACHING THROUGH THE RESOLUTION OF SPECIFIC EXERCISES OF INFORMATION REPRESENTATION, ASSEMBLER PROGRAMMING AND COMPLEX LOGIC CIRCUIT DESIGN. THE ORAL EXAMINATION IS AIMED TO ASSESS THE GENERAL PREPARATION WITH RESPECT TO THE ENTIRE PROGRAM.

Verification of learning

WRITTEN TEST AND ORAL EXAMINATION.
THERE ARE TWO IN ITINERE TESTS THAT EXEMPT THE WRITTEN TEST.
THE WRITTEN TEST AND THE IN ITINERE TESTS ARE USED TO ASSESS THE STUDENT'S ABILITY TO PRACTICE THE NOTIONS OF TEACHING THROUGH THE RESOLUTION OF SPECIFIC EXERCISES OF INFORMATION REPRESENTATION, ASSEMBLER PROGRAMMING AND COMPLEX LOGIC CIRCUIT DESIGN.
THE ORAL EXAMINATION IS AIMED TO ASSESS THE GENERAL PREPARATION WITH RESPECT TO THE ENTIRE PROGRAM.

	Texts
	DAVID PATTERSON - JOHN HENNESSY, "STRUCTURE, AND PROJECT OF COMPUTERS.", V EDITION ZANICHELLI ---- FRANCO PREPARATA, "INTRODUCTION TO THE ORGANIZATION AND DESIGN OF AN ELECTRONIC ELEBORATOR", FRANCO ANGELI ---- THE FIRST TEXT BOOK MAY POSSIBLY BE REPLACED BY THE PREVIOUS EDITION OF THE SAME: DAVID PATTERSON - JOHN HENNESSY, "STRUTTURA, ORGANIZZAZIONE E PROGETTO DEI CALCOLATORI.", IV EDIZIONE ZANICHELLI

Texts

DAVID PATTERSON - JOHN HENNESSY, "STRUCTURE, AND PROJECT OF COMPUTERS.", V EDITION ZANICHELLI
----
FRANCO PREPARATA, "INTRODUCTION TO THE ORGANIZATION AND DESIGN OF AN ELECTRONIC ELEBORATOR", FRANCO ANGELI
----
THE FIRST TEXT BOOK MAY POSSIBLY BE REPLACED BY THE PREVIOUS EDITION OF THE SAME:
DAVID PATTERSON - JOHN HENNESSY, "STRUTTURA, ORGANIZZAZIONE E PROGETTO DEI CALCOLATORI.", IV EDIZIONE ZANICHELLI

Lessons Timetable

BETA VERSION Data source ESSE3 [Ultima Sincronizzazione: 2024-11-18]

Ugo FIORE | COMPUTER ARCHITECTURE